Verilog HDL signed探索实验

##方案描述

使用Verilog语言，设计3个计数器，目的为计数值变化过程-7~7
计数器1 字长4比特，二补码数，初始计数值设置为signed 1001
计数器2 字长4比特，二补码数，初始计数值设置为signed 1111
计数器3 字长4比特，无符号数，初始计数值设置为unsigned 1001
分别验证3个计数器的计数值变化过程，是否满足初衷

###<font color= blue>Verilog HDL程序代码以及输出仿真文件
- **<font color= red>计数器1 字长4比特，二补码数，初始计数值设置为signed 1001**
- **波形仿真文件，显示计数器1的动态变化，显示方式选择为Signed Decimal in Two's Complement**
![这里写图片描述](https://img-blog.csdn.net/20170315164633385?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvcHJvdG9uX2Jva2U=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast)

```Verilog HDL
module cnt_fu7to7_signed     //cnt_counter
(		      
 CLK   ,   // clock
 CNTVAL    // output counter value
 );  
input CLK;
output [4-1:0] CNTVAL;

reg signed [4-1:0] CNTVAL; 

initial
begin
 CNTVAL <= 4'b1001;
end

always @ (posedge CLK) 
begin
  if(CNTVAL[3]== 0 && CNTVAL[2]==1 && CNTVAL[1]==1 && CNTVAL[0]==1)
   CNTVAL <= 4'b1001;
  else
    CNTVAL <= CNTVAL + 4'b0001;
end
 
endmodule  
```
----------------------------------------------
- **<font color= red>计数器2 字长4比特，二补码数，初始计数值设置为signed 1111**

- **波形仿真文件，显示计数器2的动态变化，显示方式选择为Signed Decimal in Two's Complement**
![这里写图片描述](https://img-blog.csdn.net/20170315165534426?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvcHJvdG9uX2Jva2U=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast)

- **波形仿真文件，显示计数器2的动态变化，显示方式选择为signed decimal in sign magnitude**
![这里写图片描述](https://img-blog.csdn.net/20170315170140248?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvcHJvdG9uX2Jva2U=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast)

```Verilog HDL
module cnt_fu7to7_signed     //cnt_counter
(		      
 CLK   ,   // clock
 CNTVAL,   // output counter value
 OV        //over flow
 );  
input CLK;
output [4-1:0] CNTVAL;
output OV;

reg signed [4-1:0] CNTVAL; 
reg OV;

initial
begin
 CNTVAL <= 4'b1111;
end

always @ (posedge CLK) 
begin
  if(CNTVAL[3]== 0 && CNTVAL[2]==1 && CNTVAL[1]==1 && CNTVAL[0]==1)
   CNTVAL <= 4'b1111;
  else
    CNTVAL <= CNTVAL + 4'b0001;
end

always @ (CNTVAL) 
begin
  if(CNTVAL[3]== 0 && CNTVAL[2]==1 && CNTVAL[1]==1 && CNTVAL[0]==1)
	OV = 1'b1;
  else
	OV = 1'b0;
end

endmodule  
```
-----------------------------------------------------------------
- **<font color= red>计数器3 字长4比特，无符号数，初始计数值设置为unsigned 1001**

- **波形仿真文件，显示计数器3的动态变化，显示方式选择为Signed Decimal in Two's Complement**
![这里写图片描述](https://img-blog.csdn.net/20170315172149072?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvcHJvdG9uX2Jva2U=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast)

```Verilog HDL
module cnt_fu7to7_signed     //cnt_counter
(		      
 CLK   ,   // clock
 CNTVAL,   // output counter value
 OV        //over flow
 );  
input CLK;
output [4-1:0] CNTVAL;
output OV;

reg [4-1:0] CNTVAL; 
reg OV;

initial
begin
 CNTVAL <= 4'b1001;
end

always @ (posedge CLK) 
begin
  if(CNTVAL[3]== 0 && CNTVAL[2]==1 && CNTVAL[1]==1 && CNTVAL[0]==1)
   CNTVAL <= 4'b1001;
  else
    CNTVAL <= CNTVAL + 4'b0001;
end

always @ (CNTVAL) 
begin
  if(CNTVAL[3]== 0 && CNTVAL[2]==1 && CNTVAL[1]==1 && CNTVAL[0]==1)
	OV = 1'b1;
  else
	OV = 1'b0;
end

endmodule  
```

##总结（Verilog signed 用法）：

计数器1输入为7的二进制补码，且类型设置为signed，输出显示选择补码显示，正确
计数器2输入为7的二进制原码，且类型设置为signed，输出显示选择补码显示或者有符号数显示，均错误
计数器3输入为7的二进制补码，且类型设置为unsigned，输出显示选择补码显示，正确
以上显示结果表明，signed意在向计算机说明输入数据为二进制补码，此时输出也应选择为补码显示。unsigned时，虽然结果正确，但那是因为设置输出显示为补码，只是认为的改变了它的显示方式

Verilog HDL signed探索实验

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