使用顺序语句实现38译码器以及信号赋值在顺序语句中的性质

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder38 is
port(input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(7 downto 0));
end decoder38;
architecture decoder of decoder38 is
begin
process(input) begin
output<=“00000000”;
output(CONV_INTEGER(input))<=‘1’; --这两个的交集同一信号仅为output(CONV_INTEGER(input)),大体上是不属于同一信号先后赋值的，所以不会出现没有初值的情况
end process;
end decoder;
与下例程序对比

library IEEE；
use ieee.std_logic_1164.all;
entity mux is —四选一多路选择器
port(i0,i1,i2,i3,a,b: in std_logic;
q: out std_logic);
end mux;
architecture body_mux of mux is
signal muxval : integer range 0 to 3;
begin
process(i0,i1,i2,i3,a,b) begin
muxval<=0;