VHDL实现编码器和译码器

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普通编码器（8——3编码器）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY encode8_3 IS
	PORT(input:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		output:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END encode8_3;
ARCHITECTURE encode8_3_behavior OF encode8_3 IS
BEGIN
	PROCESS(input)
	BEGIN
		CASE encode8_3 IS
			WHEN "00000001" => output<="000";
			WHEN "00000010" => output<="001";
			WHEN "00000100" => output<="010";
			WHEN "00001000" => output<="011";
			WHEN "00010000" => output<="100";
			WHEN "00100000" => output<="101";
			WHEN "01000000" => output<="110";
			WHEN "10000000" => output<="111";
			WHEN OTHERS => NULL;
		END CASE;
	END PROCESS;
END encode8_3_behavior;

优先级编码器（8——3编码器）

--优先级8——3编码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY encode8_3 IS
	PORT(input:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		output:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END encode8_3;
ARCHITECTURE encode8_3_behavior OF encode8_3 IS
BEGIN
	PROCESS(input)
	BEGIN
		IF input(7)='1' THEN
			output<="111";
		ELSIF input(6)='1' THEN
			output<="110";
		ELSIF input(5)='1' THEN
			output<="101";
		ELSIF input(4)='1' THEN
			output<="100";
		ELSIF input(3)='1' THEN
			output<="011";
		ELSIF input(2)='1' THEN
			output<="010";
		ELSIF input(1)='1' THEN
			output<="001";
		ELSIF input(0)='1' THEN
			output<="000";
		ELSE
			NULL;
		END IF;
	END PROCESS;
END encode8_3_behavior;

译码器（3——8译码器）

--3——8译码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decode3_8 IS
	PORT(input:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		output:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END decode3_8;
ARCHITECTURE decode3_8_behavior OF decode3_8 IS
BEGIN
	PROCESS(input)
	BEGIN
	CASE input IS
		WHEN "000" => output<="00000001";
		WHEN "001" => output<="00000010";
		WHEN "010" => output<="00000100";
		WHEN "011" => output<="00001000";
		WHEN "100" => output<="00010000";
		WHEN "101" => output<="00100000";
		WHEN "110" => output<="01000000";
		WHEN "111" => output<="10000000";
		WHEN OTHERS => output<="ZZZZZZZZ";
	END CASE;
END PROCESS;
END decode3_8_behavior;