register file verilog model

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1. 1 port register file verilog model

module rf1p(//input
clk,d,cs,wen,addr,
//output
q);
// parameter
parameter WIDTH =4;
parameter ADDR=2;
parameter DEPTH=4;
input clk;
input cs;
input [WIDTH-1:0] d;
input wen;
input [ADDR-1:0] addr;
output reg  [WIDTH-1:0] q;

reg chip_en;
reg [WIDTH-1:0] array [DEPTH-1:0];
always @(posedge clk) begin
if (~cs)
    chip_en<= 1'b0;
else
    chip_en <= 1'b1;
end

always @(posedge clk) begin
if(~chip_en &~wen)
    array[addr] <= d;
end

always @(posedge clk) begin
if(~chip_en &wen)
    q<=array[addr];
end

endmodule

2. testbench for writing and reading

module tb();
parameter WIDTH =8;
parameter ADDR=8;
parameter DEPTH=64;
  reg clk;
  reg cs;
  reg wen;
  reg [ADDR-1:0] addr;
  reg [WIDTH-1:0] din;
  wire [WIDTH-1:0] q;
  initial begin
    clk=0;
    cs=1;
    wen=0;
    addr=0;
    din=0;
    #10 cs=0;
    write(10,20);
    write(20,40);
    write(30,60);
    read(10);
    read(20);
    read(30);
    #100 $finish;
  end
rf1p #(.WIDTH(8),.ADDR(8),.DEPTH(64))u_rf1p(//input
.clk(clk),
.d(din),
.cs(cs),
.wen(wen),
.addr(addr),
//output
.q());
  always #5 clk=~clk;
  
  
  
  task write(//
  input [ADDR-1:0] adr,
  input [WIDTH-1:0] DIN);
  begin
    #100
    @(posedge clk);
      addr=adr;
      din=DIN;
    #1
    wen=1;
    @(posedge clk);
    #50
    wen=0;
      
  end
     
  endtask
  
  task read(
    input [ADDR-1:0] adr
  );
    begin
      #100;
          @(posedge clk);
      addr=adr;
      #1;
      wen=1'b1;
         @(posedge clk);
         wen=1'b0;
    end
    endtask
endmodule

3. waveform