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在Verilog代码中，function的语言为：
function <返回值位宽或类型说明> 函数名；
端口声明；
局部变量定义；
其他语句；
endfunction
使用函数的方法实现的数码管显示功能：
always @ (posedge clk_ww or negedge rst_n) begin
if(!rst_n)begin
Num_Disp1 <= 4'd1;
Num_Disp2 <= 4'd2;
Num_Disp3 <= 4'd3;
Num_Disp4 <= 4'd4;
smg_wei <= 4'b1111;
smg_duan <= 'd0;
wei_Scan <= 3'd0;
Count_1K <= 16'd0;
end
else begin
case(wei_Scan) //bit high 1
3'd0:begin
wei_Scan <= 3'd1;
smg_wei <= 4'b0111;
smg_duan <= SMG_Translate(Num_Disp1);
end
3'd1:begin
wei_Scan <= 3'd2;
smg_wei <= 4'b1011;
smg_duan <= SMG_Translate(Num_Disp2);
end
3'd2:begin
wei_Scan <= 3'd3;
smg_wei <= 4'b1101;
smg_duan <= SMG_Translate(Num_Disp3);
end
3'd3:begin
wei_Scan <= 3'd0;
smg_wei <= 4'b1110;
smg_duan <= SMG_Translate(Num_Disp4);
end
endcase
end
end
/*------------定义函数，译码----数码管显示-----高位为a-------*/
function [6:0] SMG_Translate;
input [3:0] Num;
reg [6:0] Num_Temp;
begin
case(Num)
4'd0: Num_Temp = 7'b1111110;
4'd1: Num_Temp = 7'b0110000;
4'd2: Num_Temp = 7'b1101101;
4'd3: Num_Temp = 7'b1111001;
4'd4: Num_Temp = 7'b0110011;
4'd5: Num_Temp = 7'b1011011;
4'd6: Num_Temp = 7'b1011111;
4'd7: Num_Temp = 7'b1110000;
4'd8: Num_Temp = 7'b1111111;
4'd9: Num_Temp = 7'b1111011;
endcase
SMG_Translate = Num_Temp;
end
endfunction将要显示的4bit数据送入函数中，函数返回的就是数码管的段选码。
虽然这样看起来代码简洁了，但不清楚这样会不会降低资源的消耗，编译结果：
使用MAXII的器件编译，使用了37个单元。
查看RTL级电路图：
接着，去掉function函数，将代码改成这样：
always @ (posedge clk_ww or negedge rst_n) begin
if(!rst_n)begin
Num_Disp1 <= 4'd1;
Num_Disp2 <= 4'd2;
Num_Disp3 <= 4'd3;
Num_Disp4 <= 4'd4;
smg_wei <= 4'b1111;
smg_duan <= 'd0;
wei_Scan <= 3'd0;
Count_1K <= 16'd0;
end
else begin
case(wei_Scan) //bit high 1
3'd0:begin
wei_Scan <= 3'd1;
smg_wei <= 4'b0111;
case(Num_Disp1)
4'd0: smg_duan <= 7'b1111110;
4'd1: smg_duan <= 7'b0110000;
4'd2: smg_duan <= 7'b1101101;
4'd3: smg_duan <= 7'b1111001;
4'd4: smg_duan <= 7'b0110011;
4'd5: smg_duan <= 7'b1011011;
4'd6: smg_duan <= 7'b1011111;
4'd7: smg_duan <= 7'b1110000;
4'd8: smg_duan <= 7'b1111111;
4'd9: smg_duan <= 7'b1111011;
endcase
end
3'd1:begin
wei_Scan <= 3'd2;
smg_wei <= 4'b1011;
case(Num_Disp2)
4'd0: smg_duan <= 7'b1111110;
4'd1: smg_duan <= 7'b0110000;
4'd2: smg_duan <= 7'b1101101;
4'd3: smg_duan <= 7'b1111001;
4'd4: smg_duan <= 7'b0110011;
4'd5: smg_duan <= 7'b1011011;
4'd6: smg_duan <= 7'b1011111;
4'd7: smg_duan <= 7'b1110000;
4'd8: smg_duan <= 7'b1111111;
4'd9: smg_duan <= 7'b1111011;
endcase
end
3'd2:begin
wei_Scan <= 3'd3;
smg_wei <= 4'b1101;
case(Num_Disp3)
4'd0: smg_duan <= 7'b1111110;
4'd1: smg_duan <= 7'b0110000;
4'd2: smg_duan <= 7'b1101101;
4'd3: smg_duan <= 7'b1111001;
4'd4: smg_duan <= 7'b0110011;
4'd5: smg_duan <= 7'b1011011;
4'd6: smg_duan <= 7'b1011111;
4'd7: smg_duan <= 7'b1110000;
4'd8: smg_duan <= 7'b1111111;
4'd9: smg_duan <= 7'b1111011;
endcase
end
3'd3:begin
wei_Scan <= 3'd0;
smg_wei <= 4'b1110;
case(Num_Disp4)
4'd0: smg_duan <= 7'b1111110;
4'd1: smg_duan <= 7'b0110000;
4'd2: smg_duan <= 7'b1101101;
4'd3: smg_duan <= 7'b1111001;
4'd4: smg_duan <= 7'b0110011;
4'd5: smg_duan <= 7'b1011011;
4'd6: smg_duan <= 7'b1011111;
4'd7: smg_duan <= 7'b1110000;
4'd8: smg_duan <= 7'b1111111;
4'd9: smg_duan <= 7'b1111011;
endcase
end
endcase
end
end这样看起来代码很啰嗦，一个always里面包裹了这么多……而且四大块的case语句几乎一致。
编译过后，发现使用资源使用数还是37。
查看RTL Viewer：和之前的完全一样
