关于Verilog HDL的一些技巧、易错、易忘点 daily record

1. 一个小细节

always@(posedge I_clk)
   begin
      if(I_rst_p)
         cnt <= 2'd0;
      else if(cnt == 2'd2)
         cnt <= 2'd0;
      else
         cnt <= cnt + 1;          
   end

always@(posedge I_clk)
   begin
      if(I_rst_p)
         O_a <= 1'b0;
      else if((cnt == 2'd1) & valid)
         O_a <= 1'b1;
      else
         O_a <= 1'b0;      
   end

always@(posedge I_clk)
  begin
     if(I_rst_p)
        O_b <= 1'b0;
     else
        O_b <= ((cnt == 2'd1) & valid);
  end
assign  valid = (cnt == 2'd1);

仿真如下：