DC 综合课程大纲

chapter1 introduction to Synthesis

1. what’s synthesis
2. steps in synthesis
3. DC_GUi Overview
4. Q&A

chapter2 Ready to synthesis

1. DC setup
2. library
3. Design object
4. TCL:element/string/list
5. Attribute
6. lab
7. Q&A

chapter3 Coding style

1. consideration when coding
2. how if-else/case/loops
3. DW integration
4. Q&A

chapter4 Environment/DRC constraint

1. what’s environment
2. budget set
3. DRC constraint
4. Q&A

chapter5 timing constraint

1. clock
2. input path constraint
3. output constraint
4. exception
5. other constraint
6. Q&A

chapter6 STA introduction

1. startpoint/endpoint timing
2. how to read timing report
3. Q&A

chapter7 run synthesis

1. synthesis script analysis
2. synthesis log ananlysis
3. lab synthesis a chip
4. Q&A