ARM memory mapping
By default the ARM has access to most on and off chip memory areas, including the DSP internal memories,EMIFA, DDR2, and the additional 128K byte on chip shard SRAM .likewise almost
all of the on chip peripherals are accessible to the ARM by default.
默认情况下，arm可以访问绝大多数的片上和片外内存区域，包括DSP的内部存储空间，EMIFA， DDR2和额外的128K共享片上SRAM，同样的，几乎全部的的片上外设，默认情况下arm都是可以访问的。
DSP memory mapping
By default ,the DSP also has access to most on and off chip memory areas, with the exception of the ARM RAM , ROM and AINTC interrupt controller.
Additionally, the DSP megamodule
includes the capability to limit access to its internal memories through its SDMA
port; without needing an external MPU unit.
默认情况下，DSP也可以访问绝大多数的片上和片外内存区域，除了arm的RAM，ROM和中断控制器。除此之外，DSP的大型模块包括在不需要外部内存保护单元的情况下，限制通过它的SDMA端口来对内置存储空间进行访问。
C674x CPU
The C674x core uses a two-level
cache-based architecture .The level 1 Program cache (L1P) is 32 KB direct
mapped cache and the Level 1 Data cache(L1D) is 32 KB 2-way set associated cache
.The Level 2 memory/cache(L2) consists of a 256 KB memory space that is shared
between program and data space . L2 memory can be configured as mapped memory,
cache or a combination of both.
C674x 使用两级缓存的机制，第一级程序缓存是32K直接映射的缓存，第一级数据缓存是32K双向关联缓存。第二季缓存是一块256K的可以被程序和数据共享的内存空间。L2内存可以被配置为映射空间，缓存或者二者的结合。