UVM REGMODEL

`ifndef MY_VSQR__SV
`define MY_VSQR__SV
class my_vsqr extends uvm_sequencer;
	my_sequencer p_my_sqr;
	bus_sequencer p_bus_sqr;
	reg_model p_rm;
 
 
	function new (string name, uvm_component parent);
		super.new(name, parent);
	endfunction
 
 
	`uvm_component_utils(my_vsqr)
endclass
 
 
`endif

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转载自blog.csdn.net/hit_shaoqi/article/details/78226283
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