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实验题目：
Laboratory Exercise 3
Registered Adder
Please design a circuit shown below,an adder with registers on the input and output ports.The adder supports unsigned numbers. Write Verilog code for this adder,and compile your code. Use timing simulation to verify the correct operation of the circuit by trying different values for numbers A and B. Explain the simulation results. Submit a pdf report including code,RTL netlist,simulation results with explanation.