在DragonOS中，为了方便调试，实现了一个简单的UART驱动程序。
https://github.com/fslongjin/DragonOS/tree/master/kernel/driver/uart原理不难，就简单讲讲吧。
uart驱动程序工作的原理就是往指定的io端口写入数据，每次传送8个bit。
其中，io端口与com口的对应关系如下：
| COM端口号 | IO端口基地址 |
| 1 | 0x3f8 |
| 2 | 0x2f8 |
| 3 | 0x3e8 |
| 4 | 0x2e8 |
| 5 | 0x5f8 |
| 6 | 0x4f8 |
| 7 | 0x5e8 |
| 8 | 0x4e8 |
每个COM口有8个寄存器，功能如下：
| UART Registers | ||||
| Base Address | DLAB | I/O Access | Abbrv. | Register Name |
| +0 | 0 | Write | THR | Transmitter Holding Buffer |
| +0 | 0 | Read | RBR | Receiver Buffer |
| +0 | 1 | Read/Write | DLL | Divisor Latch Low Byte |
| +1 | 0 | Read/Write | IER | Interrupt Enable Register |
| +1 | 1 | Read/Write | DLH | Divisor Latch High Byte |
| +2 | x | Read | IIR | Interrupt Identification Register |
| +2 | x | Write | FCR | FIFO Control Register |
| +3 | x | Read/Write | LCR | Line Control Register |
| +4 | x | Read/Write | MCR | Modem Control Register |
| +5 | x | Read | LSR | Line Status Register |
| +6 | x | Read | MSR | Modem Status Register |
| +7 | x | Read/Write | SR | Scratch Register |
The “x” in the DLAB column means that the status of the DLAB has no effect on what register is going to be accessed for that offset range. Notice also that some registers are Read only. If you attempt to write data to them, you may end up with either some problems with the modem (worst case), or the data will simply be ignored (typically the result). As mentioned earlier, some registers share a Port I/O address where one register will be used when you write data to it and another register will be used to retrieve data from the same address.
1.1.1. 设置波特率
波特率的设置是通过设置divisor来实现的，
1.1.2. 发送与接收数据
操作就是先读取标志位，确认是否端口处于忙的状态，然后从DATA_REG读取数据。
在写UART驱动程序的过程中，参考了资料：https://github.com/fslongjin/DragonOS/tree/master/kernel/driver/uart
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