功能描述
Cyclone® devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.
Cyclone®器件包含二维行和列架构来实现自定义逻辑。可变速度的 列和行互连提供LAB和嵌入式内存块的信号互连。
The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs.
逻辑阵列由LAB组成，每个LAB中有10个LE。 一个LE是逻辑的小单元提供用户逻辑的有效实现
功能。 LAB在设备上分组成行和列。Cyclone器件的范围在2,910到20,060 LE之间。
功能。 LAB在设备上分组成行和列。Cyclone器件的范围在2,910到20,060 LE之间。
M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM.
M4K RAM块是具有4K位的真正的双端口存储器块内存加奇偶校验（4,608位）。 这些块提供专门的真实双端口，简单的双端口或高达36位宽的单端口内存高达250 MHz。 这些块在设备上分组成列在某些LAB之间。 Cyclone器件提供60到288 Kbits之间嵌入式RAM。
每个Cyclone设备I / O引脚由位于该位置的I / O单元（IOE）馈送设备外围的LAB行和列的末端。I / O引脚支持各种单端和差分I / O标准，如66和33 MHz，64和32位PCI标准LVDS I / O标准高达640 Mbps。 每个IOE都包含双向I / O缓冲区以及三个用于注册输入，输出和输出使能的寄存器信号。 双通道DQS，DQ和DM引脚以及延迟链（用于对齐DDR信号）提供接口支持外部存储器件，如DDR SDRAM和FCRAM器件高达133 MHz（266 Mbps）。
Cyclone器件提供全局时钟网络和最多两个PLL。该全局时钟网络由八个全球时钟线驱动在整个设备上。 全局时钟网络可以提供设备内所有资源的时钟，如IOE，LE和内存块。 全局时钟线也可用于控制信号。 PLL提供通用时钟与时钟倍增和相移以及高速差分I / O的外部输出支持。
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, look-up table (LUT) chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within a LAB. The Quartus
®
II Compiler places associated logic within a LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency.
Figure 2–2
details the Cyclone LAB.
每个LAB由10个LE，LE携带链，LAB控制信号，一个本地组成互连，查找表（LUT）链和寄存器链连接线。 本地互连在一个LAB内LE之间传输信号。 LUT链连接将一个LE的LUT的输出传输到相邻的LE用于同一LAB内的快速连续LUT连接。寄存器链连接将一个LE的寄存器的输出传送到LAB内的相邻LE的寄存器。 Quartus®II编译器放置LAB或相邻LAB内的相关逻辑，允许使用本地，LUT链和注册链连接，用于性能和面积效率。 图2-2详细介绍了Cyclone LAB。
每个LAB由10个LE，LE携带链，LAB控制信号，一个本地组成互连，查找表（LUT）链和寄存器链连接线。 本地互连在一个LAB内LE之间传输信号。 LUT链连接将一个LE的LUT的输出传输到相邻的LE用于同一LAB内的快速连续LUT连接。寄存器链连接将一个LE的寄存器的输出传送到LAB内的相邻LE的寄存器。 Quartus®II编译器放置LAB或相邻LAB内的相关逻辑，允许使用本地，LUT链和注册链连接，用于性能和面积效率。 图2-2详细介绍了Cyclone LAB。
LAB块的互联：
The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM blocks from the left and right can also drive a LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 2–3 shows the direct link connection.
LAB本地互连可以驱动同一LAB内的LE。 LAB本地互连由列和行互连和LE输出驱动。 相邻的LAB，PLL和M4K RAM左侧和右侧的块也可以驱动LAB的本地互连
通过直接链接连接。 直接链接连接功能最小化行和列互连的使用，提供更高的性能和灵活性。 每个LE可以快速驱动30个其他LE本地和直接链路互连。 如图2-3所示连接。
通过直接链接连接。 直接链接连接功能最小化行和列互连的使用，提供更高的性能和灵活性。 每个LE可以快速驱动30个其他LE本地和直接链路互连。 如图2-3所示连接。
LAB控制信号：
Each LAB contains dedicated logic for driving control signals to its LEs.The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can also be used with other functions.
clear signals are generally used when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any LE in a particular LAB using th
labclk1
signal will also use
labclkena1
. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. Deasserting the clock enable signal will turn off the LAB-wide clock
Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high.
每个LAB都包含用于将控制信号驱动到其LE的专用逻辑。控制信号包括两个时钟，两个时钟使能，两个异步清零，同步清零，异步预置/负载，同步负载和加/减控制信号。这给了一次最多10个控制信号。虽然同步负载和他们可以在实施计数器时通常使用清除信号也可与其他功能一起使用。
每个LAB都可以使用两个时钟和两个时钟使能信号。每个LAB的时钟和时钟使能信号被链接。例如，任何一个LE使用labclk1信号的特定LAB也将使用labclkena1。如果LAB使用时钟的上升沿和下降沿，它也使用两者LAB宽时钟信号。 取消分频时钟使能信号将关闭LAB宽时钟
With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data.
使用LAB宽的addnsub控制信号，单个LE可以实现一位加法器和减法器。 这样可以节省LE资源并改善逻辑功能的性能，如DSP相关器和签名乘法器之间交替的加法和减法取决于数据。
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2–4 shows the LAB control signal generation circuit.
LAB行时钟[5..0]和LAB本地互连生成LAB宽控制信号。 MultiTrackTM互连的固有低电平倾斜除了数据之外，允许时钟和控制信号分配。LAB控制信号发生电路如图2-4所示。
