TICC3200通过TLV320AIC3254录音，录到的音频是双声道（立体声）的，因为不需要两个声道的声音，同时也减少网络传输的压力，现在想将双声道录音改为单声道录音。
首先想到是通过设置TLV320AIC3254录音芯片的寄存器，可以将双声道录音改为单声道的，于是在程序中芯片设置的地方找，找到：
//配置音频芯片的寄存器：
// Configure Audio Codec
// 配置音频芯片：
AudioCodecReset(AUDIO_CODEC_TI_3254, NULL);
AudioCodecConfig(AUDIO_CODEC_TI_3254, AUDIO_CODEC_16_BIT, 16000,
AUDIO_CODEC_STEREO, AUDIO_CODEC_SPEAKER_ALL,
AUDIO_CODEC_MIC_ALL);
//*****************************************************************************
//
//! Configure audio codec for smaple rate, bits and number of channels
//!
//! \param[in] codecId - Device id
//! \param[in] bitsPerSample - Bits per sample (8, 16, 24 etc..)
//! Please ref Bits per sample Macro section
//! \param[in] bitRate - Sampling rate in Hz. (8000, 16000, 44100 etc..)
//! \param[in] noOfChannels - Number of channels. (Mono, stereo etc..)
//! Please refer Number of Channels Macro section
//! \param[in] speaker - Audio out that need to configure. (headphone, line out, all etc..)
//! Please refer Audio Out Macro section
//! \param[in] mic - Audio in that need to configure. (line in, mono mic, all etc..)
//! Please refer Audio In Macro section
//!
//! \return 0 on success else -ve.
//
//*****************************************************************************
int AudioCodecConfig(unsigned char codecId, unsigned char bitsPerSample, unsigned short bitRate,
unsigned char noOfChannels, unsigned char speaker, unsigned char mic)
{
unsigned int bitClk = 0;
if(codecId == AUDIO_CODEC_TI_3254)
{
AudioCodecPageSelect(TI3254_PAGE_0);
if(bitsPerSample == AUDIO_CODEC_16_BIT)
{
// Set I2S Mode and Word Length
AudioCodecRegWrite(TI3254_AUDIO_IF_1_REG, 0x00); // 0x00 16bit, I2S, BCLK is input to the device
// WCLK is input to the device,
}
else
{
return -1;
}
bitClk = bitsPerSample * bitRate * noOfChannels;
if(bitClk == 512000)
{
AudioCodecPageSelect(TI3254_PAGE_0);
AudioCodecRegWrite(TI3254_CLK_MUX_REG, 0x03); // PLL Clock is CODEC_CLKIN
AudioCodecRegWrite(TI3254_CLK_PLL_P_R_REG, 0x94); // PLL is powered up, P=1, R=4
AudioCodecRegWrite(TI3254_CLK_PLL_J_REG, 0x2A); // J=42
AudioCodecRegWrite(TI3254_CLK_PLL_D_MSB_REG, 0x00); // D = 0
AudioCodecRegWrite(TI3254_CLK_NDAC_REG, 0x8E); // NDAC divider powered up, NDAC = 14
AudioCodecRegWrite(TI3254_CLK_MDAC_REG, 0x81); // MDAC divider powered up, MDAC = 1
AudioCodecRegWrite(TI3254_DAC_OSR_MSB_REG, 0x01); // DOSR = 0x0180 = 384
AudioCodecRegWrite(TI3254_DAC_OSR_LSB_REG, 0x80); // DOSR = 0x0180 = 384
AudioCodecRegWrite(TI3254_CLK_NADC_REG, 0x95); // NADC divider powered up, NADC = 21
AudioCodecRegWrite(TI3254_CLK_MADC_REG, 0x82); // MADC divider powered up, MADC = 2
AudioCodecRegWrite(TI3254_ADC_OSR_REG, 0x80); // AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A)
}
else
{
return -1;
}
// Configure Power Supplies
AudioCodecPageSelect(TI3254_PAGE_1); //Select Page 1
AudioCodecRegWrite(TI3254_PWR_CTRL_REG, 0x08); // Disabled weak connection of AVDD with DVDD
AudioCodecRegWrite(TI3254_LDO_CTRL_REG, 0x01); // Over Current detected for AVDD LDO
AudioCodecRegWrite(TI3254_ANALOG_IP_QCHRG_CTRL_REG, 0x32); // Analog inputs power up time is 6.4 ms
AudioCodecRegWrite(TI3254_REF_PWR_UP_CTRL_REG, 0x01); // Reference will power up in 40ms when analog blocks are powered up
if(speaker)
{
unsigned char reg1;
AudioCodecPageSelect(TI3254_PAGE_0); //Select Page 0
// ##Configure Processing Blocks
AudioCodecRegWrite(TI3254_DAC_SIG_P_BLK_CTRL_REG, 0x2); // DAC Signal Processing Block PRB_P2
AudioCodecPageSelect(TI3254_PAGE_44); // Select Page 44
AudioCodecRegWrite(TI3254_DAC_ADP_FILTER_CTRL_REG, 0x04); // Adaptive Filtering enabled for DAC
AudioCodecPageSelect(TI3254_PAGE_1); // Select Page 1
reg1 = 0x00;
if(speaker & AUDIO_CODEC_SPEAKER_HP)
{
//De-pop: 5 time constants, 6k resistance
AudioCodecRegWrite(TI3254_HP_DRV_START_UP_CTRL_REG, 0x25); // Headphone ramps power up time is determined with 6k resistance,
// Headphone ramps power up slowly in 5.0 time constants
//Route LDAC/RDAC to HPL/HPR
AudioCodecRegWrite(TI3254_HPL_ROUTING_SEL_REG, 0x08); // Left Channel DAC reconstruction filter's positive terminal is routed to HPL
AudioCodecRegWrite(TI3254_HPR_ROUTING_SEL_REG, 0x08); // Left Channel DAC reconstruction filter's negative terminal is routed to HPR
reg1 |= 0x30; // HPL and HPR is powered up
}
if(speaker & AUDIO_CODEC_SPEAKER_LO)
{
//Route LDAC/RDAC to LOL/LOR
AudioCodecRegWrite(TI3254_LOL_ROUTING_SEL_REG, 0x08); // Left Channel DAC reconstruction filter output is routed to LOL
AudioCodecRegWrite(TI3254_LOR_ROUTING_SEL_REG, 0x08); // Right Channel DAC reconstruction filter output is routed to LOR
reg1 |= 0x0C; // LOL and LOR is powered up
}
//Power up HPL/HPR and LOL/LOR drivers
AudioCodecRegWrite(TI3254_OP_DRV_PWR_CTRL_REG, reg1);
if(speaker & AUDIO_CODEC_SPEAKER_HP)
{
//Unmute HPL/HPR driver, 0dB Gain
AudioCodecRegWrite(TI3254_HPL_DRV_GAIN_CTRL_REG, 0x00); // HPL driver is not muted, HPL driver gain is 0dB
AudioCodecRegWrite(TI3254_HPR_DRV_GAIN_CTRL_REG, 0x00); // HPR driver is not muted, HPL driver gain is 0dB
}
if(speaker & AUDIO_CODEC_SPEAKER_HP)
{
//Unmute LOL/LOR driver, 0dB Gain
AudioCodecRegWrite(TI3254_LOL_DRV_GAIN_CTRL_REG, 0x0E); // LOL driver gain is 11dB
AudioCodecRegWrite(TI3254_LOR_DRV_GAIN_CTRL_REG, 0x0E); // LOL driver gain is 11dB
}
AudioCodecPageSelect(TI3254_PAGE_0); //Select Page 0
//DAC => 64dB
AudioCodecRegWrite(TI3254_LEFT_DAC_VOL_CTRL_REG, 0x80); // Digital Volume Control = 64.0dB silent Note: As per data sheet its reserved but on setting this value there is silent
AudioCodecRegWrite(TI3254_RIGHT_DAC_VOL_CTRL_REG, 0x80); // Digital Volume Control = 64.0dB silent Note: As per data sheet its reserved but on setting this value there is silent
AudioCodecPageSelect(TI3254_PAGE_0); //Select Page 0
//Power up LDAC/RDAC
AudioCodecRegWrite(TI3254_DAC_CHANNEL_SETUP_1_REG, 0xD6); // Left and Right DAC Channel Powered Up
// Left DAC data Left Channel Audio Interface Data
// Right DAC data is Left Channel Audio Interface Data
// Soft-Stepping is disabled
//Unmute LDAC/RDAC
AudioCodecRegWrite(TI3254_DAC_CHANNEL_SETUP_2_REG, 0x00); // When Right DAC Channel is powered down, the data is zero.
// Auto Mute disabled
// Left and Right DAC Channel not muted
// Left and Right Channel have independent volume control
}
if(mic)
{
unsigned char reg1 = 0x00; // TI3254_MICBIAS_CTRL_REG
unsigned char reg2 = 0x00; // TI3254_LEFT_MICPGA_P_CTRL_REG
unsigned char reg3 = 0x00; // TI3254_LEFT_MICPGA_N_CTRL_REG
unsigned char reg4 = 0x00; // TI3254_RIGHT_MICPGA_P_CTRL_REG
unsigned char reg5 = 0x00; // TI3254_RIGHT_MICPGA_N_CTRL_REG
unsigned char reg6 = 0x00; // TI3254_FLOAT_IP_CTRL_REG
AudioCodecPageSelect(TI3254_PAGE_8); // Select Page 8
AudioCodecRegWrite(TI3254_ADC_ADP_FILTER_CTRL_REG, 0x04); // Adaptive Filtering enabled for ADC
AudioCodecPageSelect(TI3254_PAGE_0); //Select Page 0
AudioCodecRegWrite(TI3254_ADC_SIG_P_BLK_CTRL_REG, 0x2); // ADC Signal Processing Block PRB_P2
if(mic & AUDIO_CODEC_MIC_LINE_IN)
{
reg1 |= 0x40; // MICBIAS powered up
reg2 |= 0x40; // IN1L is routed to Left MICPGA with 10k resistance
reg3 |= 0x40; // CM is routed to Left MICPGA via CM1L with 10k resistance
reg4 |= 0x40; // IN1R is routed to Right MICPGA with 10k resistance
reg5 |= 0x40; // CM is routed to Right MICPGA via CM1R with 10k resistance
reg6 |= 0xC0; // IN1L input is weakly driven to common mode. Use when not routing IN1L to Left and Right MICPGA and HPL, HPR
}
if(mic & AUDIO_CODEC_MIC_MONO)
{
reg1 |= 0x40; // MICBIAS powered up
reg2 |= 0x00;
reg3 |= 0x10;
reg4 |= 0x10; // IN2R is routed to Right MICPGA with 10k resistance
reg5 |= 0x40; // CM is routed to Right MICPGA via CM1R with 10k resistance
reg6 |= 0x10; // IN2R input is weakly driven to common mode. Use when not routing IN2R to Left and Right MICPGA
}
if(mic & AUDIO_CODEC_MIC_ONBOARD)
{
reg1 |= 0x40; // MICBIAS powered up
reg2 |= 0x00;
reg3 |= 0x04;
reg4 |= 0x04; // IN3R is routed to Right MICPGA with 10k resistance
reg5 |= 0x40; // CM is routed to Right MICPGA via CM1R with 10k resistance
reg6 |= 0x04; // IN3R input is weakly driven to common mode. Use when not routing IN3R to Left and Right MICPGA
}
AudioCodecPageSelect(TI3254_PAGE_1); //Select Page 1
AudioCodecRegWrite(TI3254_MICBIAS_CTRL_REG, reg1);
//Route IN2L not routed
AudioCodecRegWrite(TI3254_LEFT_MICPGA_P_CTRL_REG, reg2);
//Route IN2R CM1L to LEFT_N with 10K input impedance
AudioCodecRegWrite(TI3254_LEFT_MICPGA_N_CTRL_REG, reg3);
//Route IN2R to RIGHT_P with 10K input impedance
AudioCodecRegWrite(TI3254_RIGHT_MICPGA_P_CTRL_REG, reg4);
//Route CM1R to RIGHT_M with 10K input impedance
AudioCodecRegWrite(TI3254_RIGHT_MICPGA_N_CTRL_REG, reg5);
AudioCodecRegWrite(TI3254_FLOAT_IP_CTRL_REG, reg6);
//make channel gain 0dB, since 20K input
//impedance is used single ended
AudioCodecRegWrite(TI3254_LEFT_MICPGA_VOL_CTRL_REG, 0x5F); // 0.0dB
//Unmute Right MICPGA, Gain selection of 6dB to
//make channel gain 0dB, since 20K input
//impedance is used single ended
AudioCodecRegWrite(TI3254_RIGHT_MICPGA_VOL_CTRL_REG, 0x5F); // 0.0dB
AudioCodecRegWrite(TI3254_LEFT_ADC_VOL_CTRL_REG, 0x68); // -12dB 0x68
AudioCodecRegWrite(TI3254_RIGHT_ADC_VOL_CTRL_REG, 0x68); // -12dB
AudioCodecPageSelect(TI3254_PAGE_0); // Select Page 0
//Power up LADC/RADC
AudioCodecRegWrite(TI3254_ADC_CHANNEL_SETUP_REG, 0xC0); // Left and Right Channel ADC is powered up
//Unmute LADC/RADC
AudioCodecRegWrite(TI3254_ADC_FINE_GAIN_ADJ_REG, 0x00); // Left and Right ADC Channel Un-muted. Left and Right ADC Channel Fine Gain = 0dB,
}
}
return 0;
}
AudioCaptureRendererConfigure(AUDIO_CODEC_16_BIT, 16000, AUDIO_CODEC_MONO, RecordPlay, 1);
//*****************************************************************************
//
//! Initialize the AudioCaptureRendererConfigure
//!
//! \param[in] bitsPerSample - Number of bits per sample
//! \param[in] bitRate - Bit rate
//! \param[in] noOfChannels - Number of channels
//! \param[in] RxTx - Play or record or both
//! \param[in] dma - 1 for dma and 0 for non-dma mode
//!
//!
//! \return None.
//
//*****************************************************************************
void AudioCaptureRendererConfigure(unsigned char bitsPerSample,
unsigned short bitRate,
unsigned char noOfChannels,
unsigned char RxTx,
unsigned char dma)
{
unsigned long bitClk;
bitClk = bitsPerSample * bitRate * noOfChannels;
if(dma)
{
if(bitsPerSample == 16)
{
MAP_PRCMI2SClockFreqSet(512000);
MAP_I2SConfigSetExpClk(I2S_BASE,512000,bitClk,I2S_SLOT_SIZE_16|
I2S_PORT_DMA);
}
}
if(RxTx == I2S_MODE_RX_TX)
{
MAP_I2SSerializerConfig(I2S_BASE,I2S_DATA_LINE_1,I2S_SER_MODE_RX,
I2S_INACT_LOW_LEVEL);
}
if(RxTx & I2S_MODE_TX)
{
MAP_I2SSerializerConfig(I2S_BASE,I2S_DATA_LINE_0,I2S_SER_MODE_TX,
I2S_INACT_LOW_LEVEL);
}
}