[SV]SystemVerilog Cross Coverage

                          SystemVerilog Cross Coverage

   Cross Coverage is specified between the cover points or variables. Cross coverage is specified using the cross construct.

Expressions cannot be used directly in a cross; a coverage point must be explicitly defined first.

 

一、Cross coverage by cover_point name

bit [3:0] a, b;
covergroup cg @(posedge clk);
  c1: coverpoint a;
  c2: coverpoint b;
  c1Xc2: cross c1,c2;
endgroup : cg

二、Cross coverage by the variable name

bit [3:0] a, b;
covergroup cov @(posedge clk);
  aXb : cross a, b;
endgroup

   In the above example, each coverage point has 16 bins, namely auto[0]…auto[15]. The cross of a and b (labeled aXb), therefore, has 256 cross products, and each cross product is a bin of aXb.

三、Cross coverage between variable and expression

bit [3:0] a, b, c;
covergroup cov @(posedge clk);
  BC  : coverpoint b+c;
  aXb : cross a, BC;
endgroup

   The coverage group cov has the same number of cross products as the previous example, but in this case, one of the coverage points is the expression b+c, which is labeled BC.