1, ARM internal registers: CPU internal design
(1) Features: Fast
(2) Quantity: a total of 37:
6 status registers;
31 general-purpose registers (R0-R12)
R13 (SP): stack pointer, stack space in different modes is not the same
R14 (LR): link register (store breakpoint), the hardware automatically
R15 (PC): program pointer, a position instruction fetch
In the FIQ mode is independent of the other modes different
R16 PSR - CPSR (current status register)
SPSR: Program Status Register
Condition state (the NZCV) reserved word I F T bit mode (M4-M0)
SFR (Special Function Register) Special Function Register
IO port / register, which belongs to the peripheral part, ARM has is the use of a unified register addressing mode
Use a software program to control the hardware, the hardware is actually programmed to read and write registers
2, ARM exception handling
(1) and the abnormal mode
Abnormal type:
Reset: Reset
undefined instruction: undefined
swi: soft interrupt
prefect / off
data/abort
Reserved
IRQ: Interrupt
FIQ: Fast break
Processor modes: one mode corresponding to each abnormality, but not one relationship
(2) Process ARM exception handling:
Enter the exception of hardware to complete the following actions:
(1) Breakpoint: LR put inside,
Value (2) CPSR into the SPSR
Mode bit (3) modify the CPSR
(4) PC to interrupt vector (exception vector)
Software Complete the following actions:
(1) Interrupt bulk transfer, interrupt two (done by the hardware, no manual code)
(2) protect the site
(3) interrupt service routine
(4) recovery site (LR assigned to the PC, the return value SPSR CPSR)
3, the interrupt vector table
