Program Status Register (CPSR) in ARM

https://www.cnblogs.com/armlinux/archive/2011/03/23/2396833.html

WITH

Keep

Negative/Less Than

IRQ disable

WITH

Zero

FIQ disable

Carry/Borrow/Extend

State bit

Overflow

M0 ~ 4

Mode bits

1. Condition code flag

N, Z, C, and V are all condition code flags. Their content can be changed by the results of arithmetic or logical operations, and can determine whether a certain instruction is executed. The specific meanings of the condition code flags are shown in the following table:

Flag bit	Meaning
N	When performing operations with a signed number represented by two's complement, N=1 indicates that the result of the operation is negative; N=0 indicates that the result of the operation is positive or zero
WITH	Z=1 indicates that the result of the operation is zero, and Z=0 indicates that the result of the operation is non-zero.
C	There are 4 ways to set the value of C:
	-Addition operation (including CMP): When the operation result has a carry (unsigned number overflow), C=1, otherwise C=0.
	-Subtraction operation (including CMP): When a borrow occurs during operation (unsigned number overflow), C=0, otherwise C=1.
	-For non-add/subtract instructions that include shift operations, C is the last bit of the shifted value.
	-For other non-add/subtract instructions, the value of C will usually not change.
V	There are 2 ways to set the value of V:
	-For addition and subtraction instructions, when the operand and the result of the operation are signed numbers represented by binary complement, V=1 indicates that the sign bit overflows
	-For other non-add/subtract instructions, the value of V will usually not change.
Q	In E series processors of ARM V5 and above, the Q flag is used to indicate whether the enhanced DSP arithmetic instruction has overflowed. In other versions of the processor, the Q flag is undefined

In the ARM state, most instructions are conditionally executed; in the THUMB state, only branch instructions are conditionally executed.

2 control bits

The lower 8 bits of CPSR (including I, F, T, and M[4:0]) are called control bits, and these bits can be changed when an exception occurs. If the processor is running in a privileged mode, these bits can also be modified by the program.

·Interrupt disable bits I and F: When set to 1, IRQ interrupt and FIQ interrupt are prohibited.

·T flag bit: This bit reflects the operating status of the processor. When this bit is 1, the program runs in THUMB state, otherwise it runs in ARM state. This signal is reflected on the external pin TBIT. Do not modify the TBIT bit in the CPSR in the program, otherwise the processor's working state cannot be determined.

· Operating mode bits M[4:0]: These bits are mode bits, and these bits determine the operating mode of the processor. The specific meaning is shown in the following table:

·Reserved bits: The remaining bits in the CPSR are reserved bits. When changing the condition code flag bit or control bit in the CPSR, the reserved bits should not be changed, and the reserved bits should not be used to store data in the program. The reserved bits will be used for the expansion of the ARM version.

M[4：0]	Processor mode	Registers accessible in ARM mode	Registers accessible in THUMB mode
0b10000	User mode	PC,CPSR,R0~R14	PC,CPSR,R0~R7,LR,SP
0b10001	FIQ mode	PC,CPSR,SPSR_fiq,R14_fiq~R8_fiq,R0~R7	PC,CPSR,SPSR_fiq,LR_fiq,SP_fiq,R0~R7
0b10010	IRQ mode	PC,CPSR,SPSR_irq,R14_irq~R13_irq,R0~R12	PC,CPSR,SPSR_irq,LR_irq,SP_irq,R0~R7
0b10011	Management Mode	PC,CPSR,SPSR_svc,R14_svc~R13_svc,R0~R12	PC,CPSR,SPSR_svc,LR_svc,SP_svc,R0~R7
0b10111	Abort mode	PC,CPSR,SPSR_abt,R14_abt~R13_abt,R0~R12	PC,CPSR,SPSR_abt,LR_abt,SP_abt,R0~R7
0b11011	Undefined mode	PC, CPSR, SPSR_und, R14_and ~ R13_and, R0 ~ R12	PC, CPSR, SPSR_und, LR_und, SP_und, R0 ~ R7
0b11111	System mode	PC,CPSR,R0~R14	PC,CPSR,LR,SP,R0~R74

Program Status Register (CPSR) in ARM

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