In the ARM system, there are usually three ways to control the execution flow of the program:
- In the normal program execution process, each time an ARM instruction is executed, the value of the program count register PC increases by 4 bytes; each time a Thumb instruction is executed, the value of the program count register PC increases by 2 bytes. The whole process is performed sequentially.
- Through the jump instruction, the program can jump to a specific address label for execution, or jump to a specific subroutine for execution. Among them, the B instruction is used to execute the jump operation; the BL instruction saves the return address of the subroutine while executing the jump operation; the BX instruction can switch the program state to the lowest bit of the target address while executing the jump operation. Thumb state; the BLX instruction performs 3 operations, jumps to the target address for execution, saves the return address of the subroutine, and can switch the program state to the Thumb state according to the lowest bit of the target address.
- When an abnormal interrupt occurs, after the system executes the current instruction, it jumps to the corresponding abnormal interrupt handler for execution. After execution of the abort handler completes, the program returns to execution at the instruction following the instruction in which the interrupt occurred. When entering the abnormal interrupt handler, the execution scene of the interrupted program should be saved, and when exiting from the abnormal interrupt handler, the execution scene of the interrupted program should be restored.
Types of abnormal interrupts in ARM:
The abnormal interrupts in the ARM system are shown in the following table.
Various abnormal interrupts have their own backup register groups, which have been introduced in detail earlier in this chapter, and will not be repeated here.
When multiple abnormal interrupts occur at the same time, the abnormal interrupt with the highest priority can be responded to according to the priority of the abnormal interrupt. The priority of abnormal interrupt will be introduced later.
Abnormal interrupt in ARM system
| abort name | meaning |
| reset | When the reset pin of the processor is valid, the system generates a reset exception interrupt, and the program jumps to the reset exception interrupt handler for execution. The reset exception interrupt is usually used in the following situations: When the system is powered on; when the system is reset; jump to the reset interrupt vector for execution, which is called soft reset; |
| undefined directive | When the ARM processor or the coprocessor in the system thinks that the current instruction is undefined, an undefined instruction exception interrupt is generated, and the floating-point vector operation can be simulated through the exception interrupt mechanism; |
| software interrupt | This is a user-defined interrupt instruction that can be used for program-call privileged operations in user mode. |
| instruction prefetch abort | If the address of the instruction prefetched by the processor does not exist, or the address does not allow the current instruction to access, when the fetched instruction is executed, the processor generates an instruction prefetch abort exception interrupt; |
| Data access aborted | If the target address of the data access instruction does not exist, or the address does not allow the current instruction to access, the processor generates a data access abort exception; |
| External interrupt request | When the external interrupt request pin of the processor is valid, and the I control bit of the CPSR register is cleared, the processor generates an external interrupt request abnormal interrupt, and each peripheral in the system usually requests the processor service through the abnormal interrupt; |
| fast interrupt request | When the external fast interrupt request pin of the processor is valid, and the F control bit of the CPSR register is cleared, the processor generates an external interrupt request exception interrupt; |
The response process of ARM processor to abnormal interrupt:
The response process of ARM processor to abnormal interrupt is as follows.
(1) Save the current state of the processor, the interrupt mask bit and the condition flag bits. This is achieved by saving the contents of the current program status register CPSR into the SPSR register corresponding to the abnormal interrupt to be executed, and each abnormal interrupt has its own physical SPSR register.
(2) Set the corresponding bit in the current program status register CPSR. Including setting the bit in the CPSR, making the processor enter the corresponding execution mode, setting the bit in the CPSR, prohibiting the IRQ interrupt, and when entering the FIQ mode, prohibiting the FIQ interrupt.
(3) Set the register lr_mode to the return address;
(4) the program counter PC is set to the interrupt vector address of this abnormal interrupt, thereby jumping to the corresponding abnormal interrupt handler for execution;
The above-mentioned response process of the processor to the abnormal interrupt can be described by the following code:
R14_<mode> = return link
SPSR_<mode> = CPSR
CPSR[4:0] = exception mode number
CPSR[5] = 0;
if(exception_mode > reset or FIQ) then
CPSR[6] = 1
CPSR[7] = 1
PC = exception vector address
Return from the exception handler:
Returning from an exception handler consists of the following two basic operations.
(1) Restore the processor state of the interrupted program, that is, copy the contents of the SPSR_mode register to the CPSR.
(2) Return to the next instruction of the instruction in which the abnormal interrupt occurs, that is, copy the contents of the lr_mode register to the program counter PC.
The execution of the entire user program begins at the reset abort handler, so it does not need to return.
In fact, when an abnormal interrupt occurs, the position pointed to by the program counter PC is different for various abnormal interrupts, and similarly, the return address is also different for various abnormal interrupts.