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to interrupt
Interrupt (Interrupt) mechanism, that is, the processor is suddenly interrupted by other requests in the process of sequentially executing the program instruction flow and suspends the execution of the current program, and turns to deal with other things. Go back to the point where the previous program was interrupted and continue to execute the previous program instruction flow. The main points are as follows
interrupt request, interrupt source
The "other request" that interrupts the processor's execution of the program instruction flow is called an interrupt request (Interrupt Request), and the source of the "other request" is called an interrupt source (Interrupt Source). The interrupt source usually comes from the peripheral equipment.
interrupt service routine
The "other things" that the processor turns to handle are called interrupt service routines (Interrupt Service Routine ISR).
save scene, restore scene
Interrupt handling is a normal mechanism, not an error condition. After the processor receives the interrupt request, it needs to save the scene of the current program, which is called saving the scene for short. After processing the interrupt service routine, the processor needs to restore the previous scene, so as to continue to execute the previously interrupted program, which is referred to as the restoration scene.
Interrupt Arbitration, Interrupt Priority
There may be a situation where multiple interrupt sources initiate requests to the processor at the same time, so these interrupt sources need to be arbitrated to select which interrupt source is prioritized. This situation is called interrupt arbitration, and different interrupts can be assigned priorities so that Because of arbitration, there is a concept of interrupt priority for interrupts.
interrupt nesting
If the processor is processing an interrupt (in the ISR executing the interrupt), a new interrupt request with a higher priority arrives at this time, how the processor handles it in two cases
- The first possibility is that the processor does not respond to new interrupts, but continues to execute the interrupt service program currently being processed, and does not respond to new interrupt requests until it is completely completed. This is called the processor does not support interrupt nesting.
- The second possibility is that the processor suspends the current interrupt service routine, starts to respond to the new interrupt, and executes the interrupt service routine of the new interrupt, thus forming interrupt nesting (that is, the previous interrupt has not finished responding, and the Start responding to new interrupts), and the nesting level can have many levels.
Note:
- It should be noted that, assuming that the priority of the new interrupt request is lower than the priority of the interrupt being processed (or the same), regardless of whether the processor supports interrupt nesting, it should not respond to this new interrupt request. The response to a new interrupt request must be considered after the current interrupt service routine is completed (because the priority of the new interrupt request is not higher than the interrupt priority currently being processed).
abnormal
Exception (Exception) mechanism, that is, the processor suddenly encounters an abnormal event during the sequential execution of the program instruction stream and suspends the execution of the current program and turns to handle the exception. The main points are as follows
- The "exceptional things" encountered by the processor are called exceptions (Exception). The biggest difference between exceptions and interrupts is that interrupts are often an external cause, while exceptions are caused by internal events in the processor or events in program execution, such as hardware failures, program failures, illegal instructions, or execution of special system service instructions. caused, in short, an internal cause
- Similar to the interrupt service routine, the processor also enters the exception service handler.
- Similar to interrupts, multiple exceptions may occur at the same time, so exceptions also have priority, and nesting of multiple exceptions can also occur.
abnormality in a broad sense
As mentioned in the previous section, the biggest difference between interrupts and exceptions is the internal and external causes. Beyond that, interrupts and exceptions are essentially a single concept for processors.
When interrupts and exceptions occur, the processor will suspend the currently executing program, and then execute the interrupt and exception handler; when returning, the processor resumes the previously suspended program.
Therefore, the division of interrupts and exceptions is a narrow division. Broadly speaking, both interrupts and exceptions are considered to be exceptions in a broad sense. Exceptions in the broad sense of the processor are usually only divided into synchronous exceptions (Synchronous Exception) and asynchronous exceptions (Asynchronous Exception). Some processors also call exceptions in a broad sense Trap.
sync exception
A synchronous exception is an exception caused by executing or attempting to execute a program's instruction stream. The cause of this exception can be pinpointed to an executed instruction.
Another popular manifestation of synchronous exceptions is that no matter how many times the program is executed in the same environment, it can be accurately reproduced every time.
For example, if there is an illegal instruction in the program flow, the processor will generate an Illegal Instruction Exception (Illegal Instruction Exception) when the processor executes the illegal instruction, which can be precisely located at this illegal instruction and can be reproduced repeatedly.
asynchronous exception
Asynchronous exceptions are those whose cause cannot be pinpointed to an instruction.
Another popular manifestation of asynchronous exceptions is that the program is executed many times in the same environment, and the instruction PC of each exception may be different.
The most common asynchronous exception is an external interrupt. The occurrence of an external interrupt is driven by a peripheral device. On the one hand, the occurrence of an external interrupt is accidental. On the other hand, when the interrupt request reaches the processor, the processor's program instruction flow executes to Which of the instructions is contingency. Therefore, the arrival of an interruption may coincidentally encounter a certain "unfortunate instruction being executed", and this instruction becomes a "back-up man". Where its instruction PC is located, the program stops executing and turns to execute the interrupt service routine in response to the interrupt. However, when the program is executed repeatedly, it is difficult to have the exact situation where the same instruction is repeatedly "backed up".
For asynchronous exceptions, according to the state of the processor after responding to the exception, it can be divided into two types:
Precise Asynchronous Exception
It means that the state of the processor after responding to an exception can accurately reflect the boundary of a certain instruction, that is, the state of the processor after a certain instruction is executed. External interrupts are the most common exact asynchronous exception.
Imprecise Asynchronous Exception
It means that the state of the processor after responding to an exception cannot accurately reflect the boundary of a certain instruction, that is, it may be the result of a certain instruction being executed halfway and then being interrupted, or other fuzzy states. An error in reading and writing memory is a common imprecise asynchronous exception, for example, writing data to the cache, and then the cache is replaced after a long time, writing back to the external memory, but writing back to the external memory returns an error. At this time, the processor may have executed hundreds or thousands of subsequent instructions. It is impossible to accurately locate which instruction was written to the cache at this address.
exception handling process
This article mainly refers to "Teach you how to design a CPU-RISC-V processor"