Debugging of Local Bus interface between FPGA and embedded CPU

The Local Bus bus is also called the CPU bus. According to the difference in the high and low address line sequence, it can be divided into the Motorola CPU bus and the Intel CPU bus. The ancient CS51 single-chip microcomputer is a typical representative of the Intel CPU bus, and our commonly used Power PC is the Motorola CPU bus architecture, which is derived from the 60X bus (60X bus supports 64, 32, 16, 8 four optional bit width modes ). This article takes a Power PC CPU to read and write FPGA internal registers or RAM and interrupt response through the Local Bus as an example to introduce the precautions during the development process.

I remember that at the time of HINOC1.0, the Intel XScale PXA270 (ARM CPU) chip was used to interconnect the FPGA chip on the FPGA prototype, and the interface timing used was the timing of the Local Bus bus, which was the same as the interface timing between the CPU and the external asynchronous SRAM. The HINOC chip can be regarded as a peripheral of the ARM CPU, which can allocate access space such as configurable registers or RAM. The specific timing diagram is shown in the figure below. The bus includes address, chip select, and read/write signals. The figure below is a simple read sequence. Note that the so-called asynchronous means that the CPU interface bus and the corresponding FPGA interface are not synchronized, that is, the signal sent by the CPU to the FPGA does not include the clock signal, and the FPGA needs to use its own internal clock signal to collect the address, data and other signals of the CPU interface. , which can only be used after synchronization. The CPU reads the FPGA timing in the figure below. After the CPU gives the address and the read control signal, it waits for the tAA time before it can get the correct and valid data from the data bus. The tAA time can be determined by setting the registers in the PXA270. to be adjusted.