Comprehensive after-write some Verilog code during debug in, but can not find a signal of the need to debug, look at the netlist found no?
This happens because some of our intermediate signal is optimized out.
The reason is likely to be optimized away that you do this on the back of the output signal useless, I wrote this program because the process is still the middle, feature is not perfect, so do not want to put a lot of intermediate signal as an output, it is optimized out that these signals can not be found in the debug process.
How to solve this problem?
Mode 1
Add statements at the time of variable definitions:
（* keep = “true” *）
Mode 2
Front signal will keep hierarchy choose yes, or choose soft (to maintain the level at the time of synthesis), this will help you find the signal and the signal from the name you want to grab the module will not be changed.
（* keep_hierarchy = “yes” *）module fre( a, b, c, d);
or
（* keep_hierarchy = “yes” *）fre fre_inst( a, b, c, d);
Mode 3
Use front signal (* DONT_TOUCH = "{TRUE | FALSE}" *), the signal can be prevented in the synthesis be optimized away, and when the layout.
(* dont_touch = “true” *) wire a;
E.g:
