Cracking Digital VLSI Verification Interview chap.

Speaking to a Cracking Digital VLSI Verification Interview, the serial number of the public are welcome attention

Digital Logic Design

Number Systems, Arithmetic and Codes

[1] following a decimal number to convert a signed binary, octal and hexadecimal, using as few bits

a)17

b)-17

a: of the 17 division was removed to give it to 010001 binary, octal 21, hexadecimal 0x11. Note binary must be 010001 instead of 10001, can not do without the sign bit

b: The 17 binary, the original binary code bits 110001-17, the inverted complement is added to obtain a 101,111, 57 so as octal, hexadecimal 0x2f

Binary octal, triple take, Binary hex, take Four

Decimal number [2] 0x3A How much?

years = 16 ^ 1 * 3 + 10 * 16 ^ 0 = 58

[3] What is Gray, Gray code, binary code relative to ordinary What are the benefits?

Gray code is a binary code, between adjacent coded only one difference. Compared with ordinary binary code, an error occurred while incrementing the probability of even smaller. The following table is a gray code 3bit:

Decimal	Binary	Gray code
0	000	000
1	001	001
2	010	011
3	011	010
4	100	110
5	101	111
6	110	101
7	111	100

Further, since relatively small changes in Gray code bits, compared to the binary code, Gray code using even lower power consumption

[4] What is the parity bit, how to calculate?

A parity bit is added last in the sequence of binary codes, which makes the whole string of binary number 1 is even or odd. Therefore, two types of parity, odd and even parity.

Computing check bits need to be counted in the binary code 1. If an odd number, and even parity, the parity bit is 1, so that the overall number of 1 is an even number. If the number of 1 is an even number, and even parity, the parity bit is 0, so that the overall number of 1 is an even number. Similar odd parity. Parity bits are obtained by an exclusive-OR of all bits.

[5] calculating a binary number 111001 is the odd parity bit

111001 1 number is four, so the parity bit is 1, after the tape is the number of parity bits is 5 1110011,1, odd

[6] What is BCD, he and binary code What is the difference? What Decimal 27 of binary code and BCD codes are?

BCD code, also known as binary coded decimal number, BCD code can be divided into two types of code have the right code and powerless. Among them, the common right to BCD code has 8421 yards, 2421 yards, 5421 yards, no right to BCD code more than 3 yards, more than 3 cycles, Gray code. 8421BCD code is the most basic and most commonly used BCD, and four natural binary code which is similar to you for a weight of 8, 4, it is called the right to BCD code.

Bit of the 0010,7 01112 bits, the decimal code 27 is 8421BCD, 00100111, binary code is 11011

Basic Gates

[7] Which of the following are common door? why?

AND
NAND
OR
NOR
XOR

Universal door can implement any Boolean function without the use of any other type of door door. NAND gate and NOR gate are common.

[8] how to use two two-input NAND gate implementation, two-input AND gate, two-input OR gate, a NAND gate?

AND gate:

Or door:

NAND gate:

[9] how to achieve two two-input NOR gate, two-input AND gate, two-input OR gate, a NAND gate?

AND gate:

Or door:

NAND gate:

[10] using a 2: constituting the door below 1MUX

NAND gate
Two-input AND gate
Two-input OR gate
Two-input NOR gate
Two-input NAND gate
Two-input XOR gate

NAND gate:

AND gate:

Or door:

NOR gate: a NAND gate and an OR gate

NAND gate: using AND gates and NAND gate

XOR gate:

[11] Typical applications XOR gate in data communication what is?

Is typically used for error detection, e.g., parity, CRC checking, ECC. XOR gate may be a pseudo-random number generator.

[12] and the three-input NAND gate when output is zero?

All inputs are 1

[13] How to use the XOR gates implement a NAND gate

Combinational Logic Circuits

[14] Please 2: Selector achieve 41: 1 selector

[15] What is a ring oscillator? If each gate delay is 2ps, what is the frequency of the use of three NAND gates of the ring oscillator is?

The ring oscillator may be formed of an odd number of gates, NOT gates or inverters connected to the chain, the output of the last inverter is fed back to the first.

三个反相器，信号需要经过两次反馈，即2*3个反相器，振荡频率为1/(6*2ps) = 1000/12 GHz = 83.33 GHz

Sequential Circuits and State Machines

[16] 同步电路和异步电路有什么不同？

时序电路分为两种，同步时序电路和异步时序电路

同步时序电路在适中的上升沿或者下降沿改变状态和输出值。常见的例子是flip-flop，在时钟边沿根据输入改变输出。

异步时序电路的状态和输出值是根据使能信号进行控制，这更加类似于一个带有反馈的组合逻辑。

[17] 阐述建立时间和保持时间

建立时间是在时钟进行有效转换前数据信号应该保持稳定的最短时间。

保持时间是在时钟进行有效转换后数据信号应该保持稳定的最短时间。

[18] 解释什么是clock skew

时钟信号到达两个FF的时间差称之为clock skew(时钟偏斜)

例如图中两个FF的时钟，虽然是同一个时钟源，但是由于走线的延迟，导致a的时钟比b的快。

[19] 下图output delay为10ns，setup time为5ns，hold time为2ns，组合逻辑delay为10ns，请计算该电路的最大工作频率

建立时间约束为 $,即 T>=25ns ，最大工作频率为40Mhz$

[20] 触发器和锁存器的区别什么？

触发器和锁存器都是存储信息的基本单元。一个触发器或者锁存器能够存储一bit的信息。两者的主要不同点是，触发器只在时钟上升沿或者下降沿根据采样改变输出，而锁存器在enable信号拉高期间都会跟随输入。

[21] 什么是竞争？什么时候会出现？如何避免？

当输出取决于不同信号的顺序或者时序时，被称为竞争。竞争可以分为两种

实际的硬件中的竞争
仿真行为中的竞争

实际硬件中的竞争：以SR锁存器为例，当SR都是1的时候，输出为1，此时如果SR同时变成0，那么Q和Q'就会进入竞争的情况。可以通过添加合适的逻辑避免。

仿真行为中的竞争：例如下面的代码

1  always @(posedge clk or posedge reset)
2      if (reset) X1 = 0; // reset
3      else X1 = X2;
4  always @(posedge clk or posedge reset)
5      if (reset) X2 = 1; // reset
6      else X2 = X1;

由于使用了阻塞赋值，便会发生竞争的情况，通过改为非阻塞赋值可以解决

[22] 用2:1mux实现D触发器

[23] 用D触发器实现T触发器

T触发器，T为0时输出不变，1时翻转。写出真值表就能看出来，将输入和Q异或再输入到D端。

[24] 用JK触发器实现D触发器

J=D，K=D'

[25] 行波进位加法器和超前进位加法器的区别是？

行波进位加法器：

结构类似于我们拿笔在纸上做加法的方法。从最低位开始做加法，将进位结果送到下一级做和。由于本级的求和需要等待前一级的进位结果才可以得到，所以对于两个N-bit的求和。即使有N个一位的全加器，也需要N个延迟。 超前进位加法器：

事实上，在以下两种情况中，Ci=1：

Ai和Bi都为1
Ai和Bi有一个为1，且Ci-1为1

其对应的表达式为

递归后

可以看出每一级的进位信号可以不通过上一级的结果产生，只与输入有关系。因此减少了时间。

[26] 实现一个32bit寄存器需要几个flip-flop？

一个FF存储一bit信息，因此需要32个FF。

[27] mealy型FSM和moore型FSM有什么区别？

mealy型FSM的输出和当前的状态以及当前的输入有关系。

moore型FSM的输出只和当前的状态有关系。

[28] 九个状态的记录最少需要几个FF？

2^3 < 9 < 2^4，因此是4个

[29] 使用尽可能少的DFF实现二分频和四分频

二分频：

四分频：