Foreword
Began writing power amplifier circuit today
Power amplifying circuit characteristics
- To provide a sufficiently large load output power, i.e. current amplification and voltage amplification.
- Maximum output power: \ [of P_ {OM} = \ FRAC {U_upper {CEM}} {\ sqrt {2}} \ CDOT \ FRAC {of I_ {cm & lt}} {\ sqrt {2}} = \ FRAC {. 1} { CEM U_upper {}} 2 {cm & lt} of I_ \] \ (CEM} and {U_upper cm I_ {} \) are the maximum amplitude of the sinusoidal voltage and current collector output.
Efficiency of the power amplifier circuit: \ [\ ETA = \ FRAC {of P_ {O}} {P_V} \] \ (of P_ {O} \) is the amplifying circuit output to the load power, \ ({P_V} \) DC power \ (V_ {CC} \) power provided
Push-pull circuit
As shown below
can be seen from the figure, when the positive half cycle of the input signal, \ (VT1 \) is turned on, \ (VT2 \) is turned off; in the negative half cycle, \ (VT2 \) is turned on, \ (VT1 \ ) off; two transistor output signals are constantly turned on and off alternately, both outputs obtained at full load on the combined cycle. This circuit is called a push-pull circuit.
When the input voltage is zero, two transistors are turned off, the static power consumption is zero.
Plus the sinusoidal input voltage, two transistors turn ON, average power consumption is relatively small transistor, so that power is supplied more to the DC power delivered to the load.Complementary symmetry circuit OTL
By me on a write amplifier circuit and the common collector of Multisim study notes can be seen, when the load resistance is too small, the base emitter follower output waveform is truncated. To improve this disadvantage, the emitter load resistor replaced by a PNP transistor, as shown below
with a paired 2N5401 PNP type transistor instead of an emitter load resistor. npn transistor pushes current to the load, the PNP type transistor to sink current, so called push-pull emitter follower. Input and output waveforms of the circuit shown below
is visible when the load is \ (100 \ Omega \) when taken out \ (\ pm23mA \) current, but the output and the bottom waveform is not clipped. However, the \ (0V \) near the emergence of crossover distortion , because the base and the emitter voltage is less than 0.7V, the transistor is turned off, the output waveform is generated at the center \ (\ pm0.7V \) of the blind.
This eliminates the need for a transformer as an output terminal, the input terminal through a large capacitor \ (C_l \) connecting the two base of the transistor, the output terminal through a large capacitor \ (C_2 \) connected to a load, referred OTL circuit.
The above circuit OTL B complementary symmetry circuits (each of the conductive tube \ (180 [^ \ CIRC \) , the circuit is called B; written on a conductive emitter follower \ (360 \ CIRC \) , known as A type circuit; is a class AB circuit therebetween). This circuit can be measured static base potential \ (U_B = 6V \).
Further, after this test circuit, a timing when the input signal is found, there is the relationship between two base of the transistor current and load \ [I_C = \ frac {V_ {CC} / 2-U} {R_L} \] Input when a sinusoidal signal 3V, the collector current of the circuit \ [I_C {\ approx} \ FRAC-5V 6V {100} {\ Omega} = 10mA \] \ (I_C \) of the maximum current \ [I_ {cm} = \ frac {V_ {CC} / 2
-U_ {CES}} {R_L} \] in order to improve cross-occurring change circuit crossover distortion, addition of diodes to eliminate blind spots transistor, as shown below
was added after 2N4007 diode visible \ (U_ {B1} = 6.5V \) , \ ({B2} = 5.5V U_upper \) , and the emitter voltage \ (= 6V U_E \) , so that the potential difference between the base and the emitter of two transistors of \ (0.5V \) , the input signal is in \ (0V \) when changes in the vicinity, the emitter can be turned on. Visible diode drop offset transistor \ (U_upper the BE} {\) , eliminating crossover distortion. A waveform as shown below
, however, due to temperature, such that \ (U_F> U_upper the BE} {\) , the input voltage is \ (0V \) while also conducting, resulting in the flow of collector current as a load, leading to increased collector current, resulting in thermal breakdown. May be modified to form the FIG
\ (R_5 \) and\ (R_6 \) is to prevent excessive collector current at no-load, but also so that the output impedance increases.
Diode transistor instead of to give \ [U_B = U_ {3CE} = (R_3 + R_4) i = \ frac {R_3 + R_4} {R_3} \ cdot {U_ {3BE}} \] change \ (R_4 \) and \ (R_3 \) ratio, the \ (U_B \) is set to \ (2U_ 3BE} {\) , i.e. \ (1BE U_B = {} + U_upper U_upper 2BE} {\) (over that \ (U_ {3BE} = {} = U_upper 1BE U_upper 2BE} {\) , but in fact the different transistors, adjustment \ (R_3 \) or \ (R_4 \) makes \ (U_B = U_ {1BE} + U_ {2BE} \) to ).
FIG experiments on \ (U_B = 1.379V \) , the output waveform is almost close to the input voltage waveform, as shown in FIG.
Small Power Amplifier Design
例：设计电压增益\(20dB\)，输出功率\(0.2W\)以上（\(8\Omega\)负载）的功率放大器。
前置电路为共发射极放大电路，后置电路为设计跟随器，如下图
1. 确定直流电源电压
电源电压由输出功率决定\[U_o=\sqrt{P_o\cdot{Z}}=\sqrt{0.2W\times{8\Omega}}=1.26V\]\[V_{p-p}=2\sqrt{2}U_o=3.6V\]
这里选12V单电源。
2. 确定共射放大电路
负载电流峰值为\(1.8V/8\Omega=225mA\),则共射放大电路提供的基极电流为\(225mA/\beta=1.7mA\)共射极放大电路集电极电流要比其大得多，取\(10mA\)。
发射极电位取\(2V\),则发射极负载电阻为\(2V/10mA=200\Omega\)
根据第一篇讲的晶体管放大电路与Multisim仿真学习笔记，计算得\(R1\)取\(4k\Omega\)，\(R_2\)取\(12k\Omega\)。
将\(Q_4\)集电极电位定为\(7.4V\),则\[R_9=\frac{12V-7.4V}{10mA}=460\Omega\]取标称值电阻\(470\Omega\)。
取\(R_3=22\Omega\)，\(R_4=180\Omega\),则电压放大倍数约为21倍（由于损耗，需要高于要求的放大倍数）。
3. 射极跟随器偏置电路
取流过\(R_5\)与\(R_6\)的电流为\(10mA/10=1mA\)，则\[R_5=\frac{u_{BE}}{I}=\frac{0.7V}{1mA}=700\Omega\]取标称值电阻\(680\Omega\),由上面讲的可知，\(R_6\)与\(R_5\)相同即可。
4. 确定设计跟随器发射极电阻
\(R_7//R_8\)取负载电阻十分之一以下，这里取\(R_7=R_8=0.5\Omega\)In addition adjustment circuit load \ (Q_1 \) and \ (Q_2 \) emitter voltage drop to the desired value. The load current (the input signal is zero) is set to \ (30mA \) , adjustment \ (R_6 \) so that pressure drop \ (30mV (. 1 \ Omega \ times30mA) \) .
5. Multisim simulation
parameters are set for the simulation, as shown
seen \ (8 \ Omega \) load, the voltage amplification factor of the power amplifier to \ [1.277V / 125.672mV \ approx10.16 fold (calculated theoretical load voltage 1.26V, to meet the design requirements) \]
output current \ [159.645mA (theoretical peak current of 225mA, the effective value of 159mA, meet) \] output power \ [P_o = 1.277V \ times159.645mA \ approx0 .2W \]
pre-emitter amplifier circuit and the rear emitter follower as the output voltage waveform of FIG.
OCL complementary symmetry circuit
Since the output of the circuit OTL large capacitance by connecting a load, easy distortion at low frequencies, the inductive effect and large capacitance, when the phase shift with a high, and a large capacitance can not be used in integrated circuits.
The output terminal of a large capacitor is removed, two transistors are two-way with the positive and negative DC power supply, this circuit is called OCL circuit , as shown below
according to the above method learned good circuit design, the output voltage waveform of the circuit as follows shown
perfect output waveform. Well herein, this end!