Foreword
Previous wrote a very common-emitter amplifier circuit design herein, this write common-collector amplifier circuit right
transistor amplifier circuit with Multisim simulation study notes
The basic principles of a common collector amplifier circuit
The figure below shows a common-collector amplifier
common collector amplifier circuit output signal is taken from the emitter electrode, and no collector load resistor \ (R_c \) (because the output signal is taken from the emitter electrode, the collector load if left resistance, the \ (R_c \) there will be a pressure drop caused by wear and tear).
Static Analysis
The following figure shows the DC path
quiescent base current:
\ [BQ of I_} = {\ V_ {{FRAC -U_ the CC} {} {} BEQ R_b + (1+ \ Beta) R_e} \]
quiescent collector current:
\ [of I_ {CQ} \ approx {{\
beta} I_ {BQ}} {\ approx} I_ {EQ} \] collector and the voltage between the emitter:
\ [U_upper the CEQ} = {{V_ the EQ the CC} {} -I_ {R_e} \]
Dynamic Analysis
Its equivalent circuit is slightly changed
where \ (R & lt ^ \ // prime_s R_s R_b = \) , \ (R & lt ^ \ // R_L R_e prime_e = \)
current amplification factor: \ [\ DOT _i {A} = \ FRAC {\ dot {I} _o}
{\ dot {I} _i} = \ frac {- \ dot {I} _e} {\ dot {I} _b} = - (1+ \ beta) \] input voltage: \ [\ dot {U} _i =
\ dot {I} _eR ^ {\ prime} _e = (1+ \ beta) \ dot {I} _bR ^ {\ prime} _e \] output voltage: \ [\ {the U-DOT } _o = \ dot {I} _br_ {be} + \ dot {I} _eR ^ {\ prime} _e = \ dot {I} _br_ {be} + (1+ \ beta) \ dot {I} _bR ^ { \ prime} _e \]
voltage magnification: \ [\ DOT {A} _U = \ FRAC {\} _O the U-DOT {{} \} the U-DOT _i} = {- \ FRAC {(1+ \ Beta) R & lt ^ {\ prime} _e} {r_
{be} + (1+ \ beta) R ^ {\ prime} _e} \] visible common collector amplifier circuit having a current amplification, but the constant voltage gain close to 1 and less than 1 , and the output voltage and input voltage in phase, it is also known emitter follower
input resistance: \ [R_i = (BE} + R_ {(1+ \ Beta) R & lt ^ \ prime_e) // R_b \]
output resistance: \ [R_o = \ frac {r_ {be} + R ^ \ prime_s} {1+ \ beta} // R_e \]
Visible emitter follower is very high input resistance, low output resistance.
Circuit Design
The basic circuit is as follows
例：设计最大输出电压\(2V_{p-p}\)，最大输出电流为\(\pm2mA\)（\(1k\Omega\)负载）的射极跟随器。
1. 确定直流电源电压
主要考虑集电极与发射极间的饱和电压\(U_{CE}\)和该电路的最大输出电流。这里选用12V电源电压。
2. 选择晶体管
考虑最大额定值（\(I_{E}\)，\(U_{CBO}\)，\(U_{CEO}\)，\(U_{EBO}\)）。这里选用通用小信号晶体管2N5551
3. 确定发射极电流工作点
电路的最大输出电流为\(\pm2mA\)，这里取\(I_E=8mA\)。
4. 确定\(R_e\)
为分别计算和得到最佳的静态工作点，取\(U_{B}=\frac{V_{CC}}{2}=6V\)，所以\(U_E=U_{B}-U_{BE}=5.3V\)，所以\[R_E=\frac{U_E}{I_E}=\frac{5.3V}{8mA}=662.5\Omega\]取标称电阻得\(R_E=620\Omega\)。
5. 基极偏置电路的设计
由上一篇写的博客可知，\(\beta\)大约为133，所以\(I_B\)取60uA，所以\[R_2=\frac{U_B}{I_1}=\frac{6V}{0.54mA}=11.1k\Omega\]\[R_1=\frac{V_{CC}-U_B}{I_1}=\frac{6V}{0.6mA}=10k\Omega\]
为方便，两者取标称电阻\(10k\Omega\)
6. 确定耦合电容
原理与共射极放大电路相同。这里取\(C_1=50uF\)，则由\(C_1\)形成的高通滤波器截止频率\[f_{c_1}=\frac{1}{2{\pi}RC}=\frac{1}{2{\pi}\times50uF\times5k\Omega}\approx0.64Hz\]而由\(C_2\)形成的高通滤波器截止频率与负载电阻有关。这里取\(C_2=50uF\)，当接1\(k\Omega\)负载时，\(C_2\)与负载电阻形成的高通滤波器截止频率为\[f_{c_2}=\frac{1}{2{\pi}RC}=\frac{1}{2{\pi}\times50uF\times5k\Omega}\approx3.18Hz\]
7. Multisim仿真验证
设置好参数进行仿真，如下图
可见电压放大倍数接近于1，负载为\ (1K \ Omega \) , the output AC current of 1.975mA, the input voltage waveform output below
#### 8. The input and output impedance
below
was added source series resistance \ (R_s \) , change the size of the resistance, of formula \ (= U_s U_i / 2 \) , the oscilloscope waveform changes were observed, as shown above, when the \ (R_s = 5k \ Omega \ ) when, just to meet, i.e., the input impedance is obtained \ (. 5K \ Omega \) , for the partial counter circuit \ (R_1 \) and \ (R_2 \) values in parallel.
And the output impedance is extremely low
case where the output load #### 9. aggravated
when the load resistance is too small, the output waveform will be truncated at the bottom, below shows load \ (680 \ Omega \) the output voltage waveform when
FIG waveform seen \ (- 2.65V \) following the waveform is truncated. At this time, the potential below shows the emitter
because when the AC path, \ (R_e \) and parallel to the load, the maximum pressure drop at both ends \ (- I_E (R_e // R_L ) = - 8.6mA \ times310 \ Omega = - 2.666V \) , so it will not output \ (- 2.65V \) below the waveform.