HDLBits-Verilog learning record | Verilog Language-Basics (2)

9.Declaring wires | wire decl

problem:Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.

If you’re following the circuit structure in the diagram, you should end up with four assign statements, as there are four signals that need a value assigned.

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    
    wire ab_out;
    wire cd_out;
    wire abcd_out;
    assign out = (a & b) | (c & d);
    assign out_n = ~((a & b) | (c & d));

endmodule

Note:
1. `default_nettype none will be mentioned later in Vectors.
2. After running, I suddenly found that the three defined lines ab_out, cd_out, and abcd_out were not used (I really didn’t have any intention at the time, I just did it according to the rules. I didn’t think about it), after I deleted the three statements, the operation also passed. Of course, logically, even if it does not run, this is of course possible. But although this saves lines of code, if there are continuing circuit diagrams later, the logic of each line of code will be very complicated, and it does not conform to the idea of ​​modularity.
Because the expected number of lines of code is 5, it has been improved as follows.

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
   
    wire ab_out, cd_out;   //可以直接连续赋值
    assign ab_out = a & b;
    assign cd_out = c & d;
    assign out = ab_out | cd_out;
    assign out_n = ~out;

endmodule

There is no single answer, you can try more on your own

10. 7458 chip

problem：Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways.

The question part said two ways, let's try them both.
Then what is required is 2 to 10 lines
1. You may choose to use an assign statement to drive each of the output wires,
then try it, use only 2 lines, just like the previous question, one line can directly express the complete logic.

assign p1y = (p1a & p1b & p1c) | (p1f & p1e & p1d);
assign p2y = (p2a & p2b) | (p2c & p2d);

2、or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates.

	wire and1, and2, and3, and4;
	
    assign and1 = p1a & p1b & p1c;
    assign and2 = p1f & p1e & p1d;
    assign and3 = p2a & p2b;
    assign and4 = p2c & p2d;
    
    assign p1y = and1 | and2;
	assign p2y = and3 | and3;