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[Verilog Basics] Solving Traffic Light Problems with State Machines
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2023-08-06 13:34:31
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1. Title description: Design two traffic lights with a state machine, the red light lasts for 30 clks, the green light lasts for 25 clks, and the yellow light lasts for 5 clks
Idea: counter plus state machine
2. Title description: Design a traffic light with a state machine, the clock is 1MHz, the red light lasts for 30s, the green light lasts for 60s, and the yellow light lasts for 5s
Code 1: Frequency division method (generate frequency division clock)
Code 2: Frequency division method (use the frequency multiplication method to realize the frequency divider)
1. Title description: Design two traffic lights with a state machine, the red light lasts for 30 clks, the green light lasts for 25 clks, and the yellow light lasts for 5 clks
Idea: counter plus state machine
1. State combination
light1
light2
state
state transition condition
jump to
red
(100）
green
(001)
S0
The current state is S0, the count value cnt = 24
S1
red
(100&
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Origin
blog.csdn.net/claylovetoo/article/details/131344243
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