DDR3 T-type topology and Fly-by topology difference comparison and Write leveling detailed explanation
When multiple DDR3 particles are connected to the main control chip, there are usually two layout methods, T-type and Fly-by. Before comparing the advantages and disadvantages of these two layouts, let’s talk about the synchronous switching noise.
Simultaneous switching noise and ground bounce
Due to the lead inductance (parasitic inductance) between the ground pin and the ground plane inside the device, in theory, when each signal flips (0→1 or 1→0), the current change will pass through the parasitic inductance of the device Affects the ground wire (the return path of the signal). It's just that this current is very small and can be ignored. However, when these signals are accumulated, such as the simultaneous conversion (switching) of multiple integrated circuit internal drivers, large noise will be generated in the ground line. The larger the output drive current, the larger the amplitude of the noise, as shown in the figure.
Compared with the T-shaped layout, the Fly-by layout has a great advantage in reducing synchronous switching noise . The reasons are analyzed below.
T-topology
Addresses, commands, and clocks reach each DDR3 chip at the same distance, which means that the signal arrives at each DDR3 chip at the same time, and synchronous switching noise will be superimposed. At the same time, there are many branches in the wiring, which is not good for signal integrity.
The advantage is that the T-type topology does not need to do Write leveling because the address, command and clock reach each DDR3 chip at the same distance.
Fly-by
The wiring of address, command and clock passes through each DDR3 chip in turn, and the signal reaches each DDR3 chip in turn, which effectively reduces the synchronous switching noise. The branching of the signal line is reduced, and the integrity of the signal is effectively guaranteed by means of the termination resistor.
Because the address, command, and clock reach each DDR3 chip at different distances, Write leveling is required.
Write leveling。
The function of Write Leveling is to adjust the edge alignment of the DQS signal and the CLK signal at the DRAM particle end; description of the adjustment process: the DDR controller constantly adjusts the delay of the DQS signal relative to the CLK, and the DRAM chip samples the signal on the CLK pin on each DQS rising edge. Clock signal, if the sampling value is always low, all DQ[n] will be kept low to inform the DDR controller, tDQSS (DQS, DQS# rising edge to CK, CK# rising edge, which is required in the standard to be +/-0.25 tCK. tCK is the CLK clock period) The phase relationship has not been satisfied. If it is found that on a certain DQS rising edge, the CLK level sampled at this time has found a transition (from the previous low jump to high), It is considered that DQS and CLK have satisfied tDQSS at this time, and at the same time, a high is sent to the DDR controller through DQ[n], indicating that a write equalization is successful, and the DDR controller will lock the phase difference. In this way, at each DRAM side, the CLK and DQS signals seen are edge-aligned.
Referring to the figure above, write equalization trimming process:
t1: pull up ODT, enable on die termination;
t2: After waiting for tWLDQSEN time (to ensure that the ODT on the DQS pin has been set), the DDR controller sets DQS; DDR memory samples the CK signal on the rising edge of DQS, and finds that CK=0, then DQ remains at 0.
t3: The DDR controller sets DQS; DDR memory samples the CK signal on the rising edge of DQS and finds that CK=0, then DQ remains at 0.
t4: DDR controller sets DQS; DDR memory samples CK signal at the rising edge of DQS, and finds CK=1, then waits for a period of time, DDR memory sets dq signal.
The reason for adopting the above strategy: For the DDR controller, it is impossible to measure the absolute position of the clk edge and the dqs edge, so the dqs delay is continuously adjusted, and a change of clk from 0 to 1 or 1 to 0 is judged on the rising edge of dqs. Once a change is detected, write leveling stops.
The DDR3 write leveling concept diagram is not easy to understand, and it will be explained below.
From the two signals diff_DQS and DQ in the figure above, it can be seen that the CK values collected on the rising edge of diff_DQS are all 0;
add a delay to diff_DQS until the CK values collected on the rising edge of diff_DQS as shown in the figure below are all It is 1, and then the DQ output is from 0 to 1, and the write leveling is completed.
Note: In the DDR3 standard document, it is often seen in the same timing diagram that there are multiple identical signal names but different waveforms, and the waveform needs to be analyzed in conjunction with the context.
Notice:
1. The memory controller inside the CPU can only delay the DQS signal and cannot perform advanced processing, so CK must be greater than the length of the DQS signal line, otherwise tDQSS will not be satisfied.
2. Write Leveling requires the support of the main control. For the main control that does not support Write Leveling, only T-shaped layout can be used. Otherwise, DDR3 will fail to communicate or fail to reach the rated frequency, so it can only run at reduced frequency.