The first chapter, basic computer hardware
1. Conversion between hexadecimal
Test method [analysis]
This test method is the basic test sites of binary numbers, conversions between decimal, octal and hexadecimal number
Points [analysis]
Usually between unsigned binary system conversion numbers
Three-digit binary number can be converted into an octal number, four binary number can be converted into a hexadecimal number
Hexadecimal number in the English 10-15 A, B, C, D, E, F (or a-f) represented by
2. The original code, anti-code complement
Test method [analysis]
This test method is a basic test sites: 1 gives the original code or codes given anti negated original code request code. 2. a description is given, which is in line with asking (usually complement) the original anti-complement code. 3. What is the range of the original anti-complement. 4 Q. representation of the original anti-complement.
Points [analysis]
The number of the original anti-complement are unsigned binary bit bits, the highest bit is the sign bit, 0 for positive, 1 for negative. The remaining bits are data bits
In the positive, the original code symbol = = trans complement
In the negative, the inverse code is based on the original code, change the sign bit, the rest of you bitwise obtained. Anti-complement arithmetic code obtained by adding.
The original code and the inverted coding problems exist two, i.e., 0 +0 and -0 are represented. Complement solve this problem, use +0 represents 0, at the same time to represent -0 -128 with the original code and anti codes, so the range of values complement one more than the number of the original code and inverted.
3. logical operation
Test method [analysis]
This test method is a test center is given a basic logic operation formula, then the formula is determined option which is equivalent thereto
Points [analysis]
2 test sites relates to arithmetic operations, logical operations involving this test sites. Suppose there are two events, the event represented by event 1 is true, the event is represented by 0 false
Or operations, symbols +, $ \ vee $. When two events occur simultaneously, as long as an event is true (1), the result is true (1)
And operations, symbols for the $ \ times $, $ \ cdot $, $ \ wedge $. When two events occur simultaneously, the two events must be true (1), the result is true (1), otherwise the result is false (0)
Non-operation. In the computer, it can identify the two numbers 0 and 1, 0 is a non-non-arithmetic operation is 0 1,1
XOR symbol $ \ oplus $. If the value of the events A and B are different, the result is 1. If the value of the events A and B are the same, the result is 0. (Simple memory is the same as 0, is different from 1)
4. The central processor
Test method [analysis]
The basic test sites present method is able to distinguish test operator and the controller members, and the role of each member
Points [analysis]
Since the operator and the controller logic circuit configuration and closely, so that collectively the central processor (CPU)
Operator comprising:
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- ALU: arithmetic and logic operations performed
- Accumulation registers: temporarily storing data and intermediate results of arithmetic
- Data buffer: temporarily storing instructions or data fetched from memory, and if want to store an instruction or data memory, they are also temporarily stored in the data buffer register
- Condition Status Register: save the contents of the condition code arithmetic instructions, logical instructions or test results obtained. Such as carry, overflow, interrupt, zero, negative and other signs
The controller includes:
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- Program Counter: To execute an instruction, first need to be taken out from the instruction memory. It is stored in the program counter instruction address. When each instruction is acquired, the memory address plus a
- Instruction register: the instruction address obtained by the program counter, will fetch instructions from memory into the instruction register, instruction register storing instruction that is currently being executed
- The instruction decoder: instruction to be executed, it is necessary to analyze the opcode of the instruction. This work is done by the instruction decoder
- Timing means: controls the entire operation
5. Addressing
Test method [analysis]
This test method is a test center substantially from the description, can determine what addressing mode is used
Points [analysis]
Instruction includes an operation code and address code. CPU after analysis command, the data needs to be removed by the operation code address
Immediate addressing: operand address code
Direct addressing: the address code stored address of the operand is removed from main memory by the address
Indirect addressing: the address codes stored address, to find another address from main memory through the address to find the operand in main memory by a main memory address
Register Addressing: address address code is stored, is removed from the operand address register by the
Register indirect addressing: the address codes stored address, the address from the register to find another through the address to find the operand in main memory through an address register
6. pipelining
Test method [analysis]
This test method is a test center Calculations 1. The basic test pipeline, 2. Concept test pipeline technology, particularly the concept of pipeline cycles
Points [analysis]
Execution time pipeline: (t1 + t2 + t3) + (n-1) t
In the above formula t, it represents the pipeline cycle. It refers to the longest period of execution pipeline
7. The multi-level storage structure
Test method [analysis]
This test method is basically the test center to test the concept at all levels of storage devices and usage scenarios
Points [analysis]
Cache: realization rate to ease the conflict between main memory and cpu, cpu require frequent access to the main memory contents of main memory
SRAM, SRAM, the refresh circuit does not need to be able to save data to be used as Cache (Cache)
DRAM, dynamic random access memory, the need to constantly refresh circuit in order to save the data, or data will be lost, is used as the main memory
ROM, read only memory, non-volatile data
Storage memory 8.
Test method [analysis]
This test method is a test center basic test the storage device corresponding to storage used
Points [analysis]
Sequentially stores: using the tape according to the time sequential data memory read and write to, read and write operations must be performed in the order of reading
Direct storage: a hard disk, CD-ROM, in accordance with a given data storage location directly to the region, read and write data, the address, the location of
Random access memory: memory usage, refers to a random storage time regardless of the physical location of the memory cell, but the address.
Associative memory: cache use, according to content stored either as a memory address storage items
9. The main memory capacity is calculated
Test method [analysis]
This test method is a test center substantially the capacity of a memory test, belonging calculation problems
Points [analysis]
Main memory using a random storage memory, required for addressing each memory cell
The so-called addressing i.e. with a hexadecimal number is represented a memory cell.
The storage unit is similar to a house, the house has a house number (which is addressed), the house also has a number (that is, the capacity of the storage unit) can accommodate the number of people.
Byte addressing, showing the memory cell capacity is measured in bytes, a byte of eight bit. Addressing by word, the memory cell capacity is expressed in units of words, and the word is a multiple of bytes (see the description of how the title).
Each memory cell is the total combined capacity of the main memory.