Soft test senior system architect designer (1) computer hardware

[Original Link] Soft Examination Senior System Architecture Designer (1) Computer Hardware

1.1 Computer hardware composition

1.1.1 Basic hardware components of a computer

• calculator
• controller
• memory
• input device
• output device

1.1.2 Central Processing Unit (CPU)

Components of a central processing unit (CPU)

• calculator
• controller
• register set
• internal bus

Functions of the Central Processing Unit (CPU)

• program control
• operation control
• time control
• data processing

The composition of the calculator

• Arithmetic Logic Unit (ALU)
• Accumulation Register (AC)
• Data Buffer Register (DR)
• Status Condition Register (PSW)

The composition of the controller:

• Instruction Register (IR)
• Program Counter (PC)
• Address Register (AR)
• Instruction Decoder (ID)

1.1.3 Memory

• Internal memory
  High speed, small capacity, generally used for temporary storage of programs, data and intermediate results
• External memory
  has a large container volume and slow speed, and can store programs and data for a long time

1.1.4 External devices

• Input device
  for inputting raw data and various commands
• Output device
  used to output the running results of the computer

1.2 Check code

1.2.1 Yard distance

The number of digits required to change from code A to code B becomes the code distance

1.2.2 Parity code

• Odd parity
  Add 1 parity bit in the code, so that the number of 1 in the code is an odd number
• Even parity
  Add 1 parity bit in the code, so that the number of 1 in the code is an even number

1.2.3 Cyclic Redundancy Check Code (CRC)

Calculation steps of cyclic redundancy check code CRC

• Add n 0s after the original information bit (n is the highest order of the generating polynomial)
• Calculate the divisor from the generator polynomial
• The original information bits are continuously divided by the divisor (the division calculation rule is actually an XOR operation) to obtain the remainder. The number of remainder digits is the highest order number of the generator polynomial, and if it is insufficient, add 0 in front
• The cyclic redundancy check code is obtained by appending the remainder to the original information bits

1.3 Command system

1.3.1 Composition of computer instructions

• opcode
• operand

1.3.2 Execution process of computer instructions

• fetch instruction
• analysis instruction
• execute command

1.3.3 Addressing Modes of Instructions

• sequential addressing mode
• jump addressing mode

1.3.4 Addressing Modes of Instruction Operands

• immediate addressing mode
• direct addressing mode
• indirect addressing mode
• Register Addressing Mode
• base addressing mode
• indexed addressing mode

1.3.5 Features of Complex Instruction System CISC

• high number of instructions
• Instruction usage frequency varies greatly
• command variable length format
• Support multiple addressing methods
• Realized by microprogram control technology
• Long development cycle

1.3.6 Features of RISC

• low number of instructions
• Instruction usage frequency close to
• Command fixed-length format
• Supports few addressing modes
• Rely on hardware implementation (controlled by registers and hardwired logic)
• Optimized compilation, effective support for high-level languages

1.3.7 Pipeline technology in RISC

• super pipelining
• superscalar technology
• Very Long Instruction Word Technology

1.3.8 Pipeline time calculation

• Pipeline cycle
  Instructions are divided into different execution segments, and the segment with the longest execution time is the pipeline cycle
• Pipeline execution time
  Total execution time of one instruction + (total number of instructions - 1) * pipeline cycle
• Pipeline throughput rate
  Number of instructions/pipeline execution time
• Speedup ratio of pipeline
  Execution time without pipeline / Execution time with pipeline

1.4 Storage system

1.4.1 Two-level storage of the storage system

• Cache-main memory
• main memory - auxiliary memory

1.4.2 Locality principle of storage system

• The principle of time locality
  The same data item will be accessed in adjacent times
• The principle of spatial locality
  Adjacent space addresses will be accessed consecutively

1.4.3 Address Mapping

The meaning of address mapping

Convert the main memory address to the Cache memory address. The conversion of this address becomes the address mapping, and the address mapping is automatically completed by the hardware.

Method of Address Mapping

• direct mapping
• fully connected map
• Group Associative Mapping

1.4.4 Cache replacement algorithm

• random replacement algorithm
• first in first out algorithm
• Least Recently Used Algorithm
• Optimal Replacement Algorithm

1.4.5 Disk scheduling algorithm

• First come first serve FCFS
• Shortest seek time first SSTF
• Scanning Algorithm SCAN
• One-way Scan Scheduling Algorithm CSCAN

1.5 Input/Output Technology

1.5.1 Addressing method of memory and interface address

• Independent Addressing Method
• Uniform Addressing Method

1.5.2 Data interaction between computer and peripherals

• Program control (query) mode
• Program interrupt mode
• DMA mode (direct main memory access)

1.6 Bus structure

1.6.1 Bus

A bus refers to a common data channel for transferring information between computer devices and devices

1.6.2 Bus classification

• internal bus
• system bus
• external bus

1.6.3 System Bus Classification

• Data Bus
• address bus
• control bus

New book launch: Pytest enterprise-level application practice