Clock Divider

50% duty cycle division:

  Even frequency division, a counter can handle;

  Odd division:

  1. The two counters respectively in accordance with the rising and falling edges counted, if the final ratio of the high level is a low level period with a plurality of gates, or with at least one cycle of the gate;







   2. Another form of use of a combination of exclusive OR gates as shown below:







       The first rising edge of the count (used only one counter) counted from 0 to (N-1)

       Then generates two enable signals tff_1en, tff_2en, wherein tff_1en count 0 is enabled, tff_2en the count to the (N + 1) / 2 to enable

      Divided clock is then generated according tff_1en div1 and rising edge generating divided clock div2 according tff_2en and falling;

      The last two frequency-divided clock XOR on OK, to give a 50% duty cycle count divider;

Non-duty ratio of 50% (non-integer division):

  For example in the form of frequency division N + 0.5, 0.5 + 5 if we can divide the counter counting on a rising falling edge respectively to 2N + 1, the high level period of N + 1, and let the two dividing up;



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