The clock output by the AHB divider is sent to 5 major modules for use:
1. The HCLK clock used by the AHB bus, core, memory, and DMA.
2. The timing clock (tick timer) sent to the system timer by dividing by 8.
3. Idle clock PCLK directly sent to Cortex.
4. The frequency divider sent to APB1 can be divided by 1, 2, 4, 8, and 16, its output is one way for APB1 peripherals (PCLK1, maximum frequency 36M) and the other way is sent to timers (timer) 2, 3, 4 frequency multiplier is used. The frequency multiplier can choose 1 or 2 multiplication, and the clock output is for timer 2, 3 and 4.
5. Sent to APB2 frequency divider can choose 1, 2, 4, 8, 16 frequency division, its output is one way for APB2 peripherals (PCLK2, maximum frequency 72M) and the other way is sent to timer (Timer) 1 frequency multiplier use. The frequency multiplier can choose 1 or 2 times. The clock output is used by Timer 1. In addition, the APB2 divider has one output for the ADC divider, which is divided and sent to the ADC module. The ADC divider can be divided into 2, 4, 6, or 8. Technical training QQ754634522
connected to APB1 (low-speed peripherals) devices include: power interface, backup interface, CAN, USB, I2C1, I2C2, UART2, UART3, SPI2, window watchdog, TIMER2, TIMER3, TIMER4.
The devices connected to APB2 (high-speed peripherals) include: UART1, SPI1, Timer1, ADC1, ADC2, all ordinary IO ports, and second function IO ports.
The above means: the clock output by the AHB divider is sent to the 5 major modules for use:
1. The HCLK clock used by the AHB bus, core, memory, and DMA.
Explain that the clock output by the AHB divider includes HCLK. Refer to many places in the tutorial during class time to directly use HCLK as the output clock of the AHB divider: for example
| PPRE1[2:0]: Low-speed APB prescaler (APB1) (APB low-speed prescaler (APB1)) is set to '1' or cleared to '0' by software to control the prescaler coefficient of the low-speed APB1 clock (PCLK1). Warning: The software must ensure that the APB1 clock frequency does not exceed 36MHz. 0xx: HCLK not divided by 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 |
Can anyone give a clear explanation?
It is puzzling that the relationship between the clock and HCLK after AHB prescaler should be the same or synchronous and equal in size. The system clock configuration in the reference manual clock configuration register and system_stm32f10x.c directly use HCLK as the AHB prescaler clock.