System timing requirements for the design of the clock signal is very strict, because all of our series calculations are based on a constant clock signal as a reference. However, the actual clock signal is often not always so perfect, there will be jitter (Jitter) and offset (Skew) problem.
The so-called jitter (Jitter), refers to the difference between two clock cycles, the errors are generated in the internal clock generator, and the internal oscillator or the PLL circuit related to no effect on the wiring. As shown below:
In addition, since the duty cycle there is a change signal jitter caused called half-cycle jitter. In general, jitter can be considered uncertain and occasional sum variation of the clock signal itself some transmission process.
Clock skew (skew) refers to a plurality of sub-delay difference between the clock signals generated by the same clock. It represents many forms, both comprising a plurality of offset between the output of the clock driver, also comprising an offset between the drive end and a receiving end clock signal since errors caused PCB traces.
Refer to the same clock skew a clock signal arrival time difference between two different registers, clock skew always there, to a certain extent it will seriously affect the timing circuit. As shown below:
Timing signal integrity, such as crosstalk will affect the propagation delay microstrip line; data signal reflection causes fluctuations near the threshold logic gate, thus affecting the maximum / minimum time of flight; clock traces interference may cause some clock skew. Some error or uncertainty in the simulation is unpredictable, the designer only to gradually increase the level of system design through the accumulation of careful thinking and practical experience.
Clock skew and Clock jitter is the main factor affecting the stability of the clock signal. Many books are from different angles inside them explained.
Wherein the interpretation "see" a book gives the most essential:
Clock Skew: The spatial variation in arrival time of a clock transition on an integrated circuit;
Clock jitter: The temporal vatiation of the clock period at a given point on the chip;
Briefly, skew is generally uncertain on the clock phase, and the jitter refers to the uncertainty (Uncertainty) on the clock frequency. Cause skew and jitter
A lot of reasons. Since the clock source to different positions in different registers experienced driver and load paths, the clock edges vary, thus bringing
skew. And stability reasons, power supply and temperature variations caused by the crystal itself, the clock frequency is changed, that is, jitter.
Effects of jitter and skew of the circuit may be a simple model to explain time. Hypothesis T (CQ) represents the maximum delay of the output register FIG.
t (cq, cd) represents the maximum output delay; t (su) and t (hold) represent the register setup, hold time (not to consider pvt) difference; t (logic)
And t (logic, cd) represent the maximum and minimum transmission delay combinational logic combinational logic propagation delay;
In the case without consideration of skew and jitter, and t (clk1) and t (clk2) same frequency and phase, and the clock period T t (hold) needs to satisfy
T > t(c-q) + t(logic) + t(su)
t(hold) < t(c-q, cd) + t(logic, cd)
So as to ensure the normal function of the circuit, and to avoid competition. Considering CLK1 CLK2 phase later than t1, and skew = t1.
则 t(hold) < t(c-q, cd) + t(logic, cd) - t1
This means that hold time violation generating circuit from greater tendency; consideration CLK1 CLK2 phase later than t2, and skew = -t2,
则 T > t(c-q) + t(logic) + t(su) + t2
This means that the circuit performance declined, but because R2 always meet the hold time, so there is no competition problems exist. clock jitter
Always a negative impact on the performance of the general design requires special specimens from about 10% margin to be guaranteed.
clock uncertainty = clock jitter + clock skew. jitter is the jitter produced by clock source. It is the difference in arrival delay skew register two clock tree to unbalance. After cts, skew is calculated by the tool, so sta clock uncertainty can be provided when a relatively small value. In addition, when do hold check because the check is the same clock edge, so there is no jitter only skew.
