STM32F103ZET6 GPIO use

1, GPIO Profile

　　A plurality of GPIO STM32F103ZET6 groups, such as GPIOA, GPIOB, GPIOC ... and so on. Each group has 16 GPIO ports IO.

　　GPIO register group are similar, each group has two GPIO configuration register 32, two 32-bit data registers, a 32-bit set / reset register, a 16-bit register and a reset 32-bit lock register.

　　Many STM32 IO ports are 5V compatible, what specific IO port is 5V compatible, can be found from the data sheet Pin description chips, it is compatible with 5V level IO Level bid FT manual in.

2, GPIO configuration

　　STM32F103ZET6 can register the CRL and CRH IO configured by configuring different functions. IO has a different following modes:

• • Floating input
  • Input drop-down
  • Input pull
  • Analog Input
  • Open-drain output
  • Push-pull output
  • Push-pull multiplexing function
  • Open drain multiplexing function　　

　　Every 4 BIT CRH and CRL register used to configure a function of IO, CRL to configure the lower 8 bits IO functions, CRH to configure the upper 8 bits IO function.

　　CNF1, CNF0, MODE1, MODE0 four bits of a configuration bits IO, as GPIOF0 configuration bits CNF1, CNF0, MODE1, MODE0 These bits are located CRL register BIT3 ~ BIT0; GPIOF1 configuration bits CNF1, CNF0 , MODE1, MODE0 these bits are located CRL register BIT7 ~ BIT4; GPIOF8 the configuration bits CNF1, CNF0, MODE1, MODE0 these bits are located CRH register BIT3 ~ BIT0; and so on. CRL and CRH these two registers 64 a total of BIT, composed of a total of 16 bits of IO configuration.

　　IO port configuration table as follows:

　　MODE0 and MODE1 are used to configure the input and output state of the IO; CNF0 CNF1 and are different depending on the configuration of the input and output states of the IO port IO functionality.

　　When configuring the IO, IO by MODE1 first configure and MODE0 input or output, and then through CNF1 CNF0 IO configuration is what input or output functions.

　　By CNF1, CNF0, MODE1, MODE0 IO these bits may be set to pull-up / pull-down input, but is specifically arranged to pull the pull-down input or inputs, according to these four bits are not determined. IO port is provided in the end it is to distinguish between the pull-down or pull-input data input by the ODR register. If the ODR IO port is set to 1, then the IO port is provided to pull the input; ODR if the IO port is cleared to 0, then the IO port is set to the pull-down input.

　　CNF1, CNF0, MODE1, MODE0 bit configuration functions as follows:

　　MODE1 MODE0 and control inputs and outputs of the IO:

• • • [MODE1, MODE0] = 00 is provided as an input.
    • [MODE1, MODE0] = 01 is set to output a rate of 10MHZ.
    • [MODE1, MODE0] = 10 is set to output a rate of 20MHZ.
    • [MODE1, MODE0] = 11 is set to output a rate of 50MHZ.

　　CNF1, CNF0 the need to distinguish The IO is input or output:

　　　　IO is set to enter:

• • • • [CNF1, CNF0] = 00 to set the input mode.
      • [CNF1, CNF0] = 01 to floating input.
      • [CNF1, CNF0] = 10 to pull-up / pull-down input.
      • [CNF1, CNF0] = 11 Reserved.

　　　　IO is set to output:

• • • • [CNF1, CNF0] = 00 to output a generic push Free.
      • [CNF1, CNF0] = 01 to common open-drain output.
      • [CNF1, CNF0] = 10 to push Free multiplexed output function.
      • [CNF1, CNF0] = 11 is set to open-drain output multiplex function.

3, GPIO reset state

　　After chip power-on reset, most of the IO port mode defaults to floating input mode. But some special IO, such as PA15, PA14, PA13, PB4, PB3 and other IO, the IO is JTAG download and debug SWIO mouth, after a chip reset, these become the default JTAG IO was SWIO and other functions, that is to say the chip after reset, PA15, PA14, PA13, PB4, PB3 IO and the like can not be provided by conventional configuration corresponding function. If you need to use IO port function of these ports, you must remap these IO functions as a GPIO port.

　　需要注意的是如果将PA15、PA14、PA13、PB4、PB3等口重映射为GPIO口后，则不能用调试器调试程序，而且也不能下载程序，只有通过复位芯片，使这些IO口的功能处于复位默认功能，才能下载程序。

　　复位后，PA15、PA14、PA13、PB4、PB3这些引脚被配置成如下模式：

• • PA15：JTDI被置为上拉输入模式。
  • PA14：JTCK/SWCLK被置为下拉输入模式。
  • PA13：JTMS/SWDIO被置为上拉输入模式。
  • PB4：JNTRST被置为上拉输入模式。
  • PB3：JTDO

4、GPIO锁定机制

　　GPIO的锁定机制允许冻结IO口的配置。当在一个端口位上通过LCKR寄存器执行了锁定（LOCK）程序，在下一次复位之前，将不能再更改端口位的配置。

5、外设的GPIO配置

　　可以在中文参考手册的GPIO介绍章节查到外设的GPIO设置，比如说如果要使用USART_TX功能，需要将USART_TX脚位配置成什么状态，可以在参考手册中查到。

6、GPIO寄存器

　　CRH和CRL是GPIO的配置寄存器，用来配置IO的功能。

　　IDR是GPIO的输入数据寄存器。通过IDR寄存器可以读出IO的状态。需要注意的是IDR寄存器只能以字（16位）的形式读出。

　　ODR是GPIO的输出数据寄存器。通过ODR寄存器可以输出高低电平。

　　BSRR是GPIO的端口位设置/清除寄存器。BSRR寄存器的高16位是清除IO位，低16位是置位IO位。需要注意的是BSRR只有在写入1的时候，相应的功能才有作用，写入0是无效的。

　　BRR是GPIO的端口位清除寄存器。BRR基础只有在写入1的时候，相应的功能才有作用，写入0无效。

　　LCKR是GPIO的端口配置锁定寄存器。LCKR寄存器用来锁定IO口的配置，设置后，除了复位后不能再配置IO的状态。

7、HAL库操作GPIO