Driven by the internal watchdog LSI, LSI is an internal RC clock is not accurate 32kHz, however, the watchdog time requirements inaccurate, and therefore may be received;
Keyword register IWDG_KR:
Open write 0xCCCCH independent watchdog, this time counter begins counting from the reset value 0xFFF, a reset signal is generated when the counter (IWDG_RESET) when 0x000;
0x5555H write and enable access to IWDG_PR IWDG_RLR register;
The value written 0xAAAAH IWDG_RLR reloaded into the counter so as to avoid watchdog reset, while the write-protect;
Prescale Register IWDG_PR:
Set Watchdog division ratio, a minimum of 4 and a maximum of 256;
Reload registers IWDG_RLR:
Save reload the value in the counter, only the lower 12 bits are valid;
Independent watchdog configuration:
Cancel write protection register;
The Watchdog prescaler reload value;
Reload counter feed the dog; (core)
Start watchdog;