(STM32) NVIC (Nested vectored interrupt controller) 學習

NVIC ARM Cortex-M is part of the processor. Responsible for handling exceptions and interrupts related procedures.

• Allow nested interrupts, interrupt, can also be interrupted
• Interrupt can be freely set, allocate resources according to their own applications
• Can interrupt mask, that is, you can disable some interrupts

priority

In Cortex-M, the smaller the numerical value representative of the higher priority.

• group priority (preempt priority)
• subpriority

Rule is a exception handler is executing, when other exceptions occur, if the group priority priority can jump the queue to perform another job than you, if you like, or lower than you, you have to obediently and so on.

If there are multiple exceptions of the same priority are waiting to be executed (the Pending) , then the first comparison subpriority, higher priority standing in the front, if still the same Exception Nmber small priority.

 

STM32 interrupt priority register (Interrupt Priority Registers)

STM32 Each Interrupt Channel has interrupt priority register their own, STM32 each priority register is a four bit, this 4-bits can be divided into the following five groups based on function

NVIC_PriorityGroup_0 => 0 bits for pre-emption priority, 4 bits for subpriority 　

NVIC_PriorityGroup_1 => 1 bits for pre-emption priority, 3 bits for subpriority 　

NVIC_PriorityGroup_2 => 2 bits for pre-emption priority, 2 bits for subpriority 　

NVIC_PriorityGroup_3 => 3 bits for pre-emption priority, 1 bits for subpriority 　

NVIC_PriorityGroup_4 => 4 bits for pre-emption priority, 0 bits for subpriority 　

NVIC_PriorityGroup	Preemption Priority	Subpriority
NVIC_PriorityGroup_0	0 (one set)	From 0 to 15 (16 species set)
NVIC_PriorityGroup_1	0,1 (two settings)	0-7 (eight settings)
NVIC_PriorityGroup_2	0, 1, 2, 3 (four settings)	0, 1, 2, 3 (four settings)
NVIC_PriorityGroup_3	4, 5, 6, 7 (eight settings)	0,1 (two settings)
NVIC_PriorityGroup_4	From 0 to 15 (16 species set)	0 (one set)

 

When we interrupt the use of the STM32 NVIC will find that interrupt priority level is divided into two kinds of preemption priority and subpriority and these two priority What is the difference:

1. Preemption Priority

    When an interrupt occurs, have a higher Preemption priority = interrupt channel 0 can be lower preemptrion priority = interrupt chnannel 1,2,3 interrupt priority is processed. If two interrupt channel with the same peemption priority, after the interrupt event to be processed must wait until after the current interrupt is processed.

　

2. Subpriority　

     In the same two interrupt channel premise of preemption priority, if two subpriority different interrupt event Tongshifasheng, the subpriority high interrupt will be processed first, but if a low-priority interrupt channel event already in progress, it can not be interrupted, high subpriority the event must wait until the current event being processed in order to be processed.

 

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
NVIC_InitStruct.NVIC_IRQChannel = EXTI0_IRQn;
NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 0x01;
NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0x04;
NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStruct);

NVIC_InitStruct.NVIC_IRQChannel = EXTI15_10_IRQn;
NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 0x01;
NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0x03;
NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStruct);

If the above example the first implementation EXTI0 trigger EXTI15_10, will give priority to the implementation of EXTI15_10

But if EXTI0 priority higher than EXTI15_10 but also triggers, EXTI0 execution will wait before executing those EXTI15_10.