STM32 NVIC interrupt priority management
The CM3 core supports 256 interrupts, including 16 core interrupts and 240 external interrupts, and there are 256 programmable interrupt settings.
But STM32 does not use all of the CM3 core, only a part of it.
STM32 has 84 interrupts, including 16 core interrupts and 68 maskable interrupts, with 16 levels of programmable interrupt priority.
Registers related to NVIC
typedef struct
{
__IOM uint32_t ISER[8U];
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U];
uint32_t RSERVED1[24U];
__IOM uint32_t ISPR[8U];
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U];
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U];
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U];
uint32_t RESERVED5[644U];
__OM uint32_t STIR;
} NVIC_Type;
ISER[8]: Interrupt enable register set. The CM3 core supports 256 interrupts, which are controlled by 8 32-bit registers, and each bit controls an interrupt.
But STM32F103 has only 60 maskable interrupts, so for us, two ISER[0] and ISER[1] are useful, which can represent a total of 64 interrupts.
Bit0~bit31 of ISER[0] correspond to interrupt 0~31 respectively. Bit0~27 of ISER[1] correspond to interrupts 32~59; so a total of 60 interrupts are corresponding to each other. If you want to enable an interrupt, you must set the corresponding ISER bit to 1 to enable the interrupt (this is only to enable, but also to cooperate with interrupt grouping, masking, IO port mapping and other settings to be a complete interrupt setting ).
ICER[8]: Interrupt disable register set.
ISPR[8]: Interrupt suspension control register group, by setting 1, the ongoing interrupt is suspended, and the interrupt of the same level or higher level is executed. Writing 0 has no effect.
ICPR[8]: The full name is: Interrupt Clear-Pending Registers, which is an interrupt release control register group. Its function is opposite to ISPR, and the corresponding bit is the same as ISER. By setting 1, the pending interrupt can be unhooked.
IABR[8]: The full name is: Interrupt Active Bit Registers, which is an interrupt activation flag bit register group. The interrupt represented by the corresponding bit is the same as ISER, if it is 1, it means that the interrupt corresponding to this bit is being executed. This is a read-only register, through which you can know which interrupt is currently executing. It is automatically cleared by hardware after the interrupt is executed.
IP[240]: The full name is: Interrupt Priority Registers, which is a register group controlled by interrupt priority. This register set is very important! The interrupt grouping of STM32 is closely related to this register group. The IP register group is composed of 240 8-bit registers, and each maskable interrupt occupies 8 bits, so that a total of 240 maskable interrupts can be represented. The STM32 only uses the first 60 of them. IP[59]~IP[0] correspond to interrupt 59~0 respectively. The 8 bits occupied by each maskable interrupt are not fully used, but only the upper 4 bits are used. These 4 bits are further divided into preemptive priority and sub-priority. The preemption priority comes first, and the sub-priority comes after. How many bits each of these two priorities occupy depends on the interrupt grouping settings in SCB->AIRCR.
interrupt packet
STM32 divides interrupts into 5 groups, group 0~4.
For example, when the group is set to 3, all 60 interrupts at this time, the highest 3 bits of the high four bits of the interrupt priority register of each interrupt are the preemptive priority , the lower 1 bit is the response priority.
For each interrupt, you can set the preemption priority to 0~7, and the response priority to 1 or 0.
Preemption priority is at a higher level than response priority. The smaller the value, the higher the priority.
If the preemption priority and response priority of the two interrupts are the same, whichever interrupt occurs first will be executed first. A high priority preemptive priority can interrupt an ongoing low preemptive priority interrupt. While preempting interrupts with the same priority, the high-priority response priority cannot interrupt the low-response priority interrupt.