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Note: This blog post is just another repetition of the Punctual Atomic Course. It summarizes punctual tutorials and writes some insights, not plagiarism in the name of originality.
One, introduction of STM32F4 interrupt
1. Number and type of STM32F4 interrupts
The core of STM32F4 is ARM's Cortex-M4 . The real Cortex-M4 supports 256 interrupts, including 16 core interrupts and 240 external interrupts , and has 256-level programmable interrupt settings ;
However, STM32F4 does not use all the Cortex-M4 interrupts, but only a part of it. There are 92 interrupts in total, including 10 core interrupts and 82 maskable interrupts . It has 16 levels of programmable interrupt priority. We often use these 82 maskable interrupts .
2. What are kernel interrupts and external interrupts?
Reference: CSDN blogger [dgergeg] article: external interrupt and internal interrupt
External interrupt refers to the interrupt program executed by the external interrupt source , mainly refers to INT0, INT1, communication interrupt; internal interrupt mainly refers to the interrupt executed by the relevant special registers such as timer/counter interrupt, set after stack overflow ;
For example, external interruption: You are eating, and the phone rang at this time. You temporarily put down the utensils to answer the phone. Eating here is the program you are currently executing. The phone rang is an interrupt source. It is random. No Occurs regularly, after answering the call (processing the interruption event) you come back and continue eating, (continue to execute the program that has not been processed at the
interruption point) internal interruption: you are eating, and there is no more rice in the bowl at this time, you are going to serve the meal , I have the rice and come back and continue to eat. Eating here is still a program you are currently working on. The absence of rice in the bowl is equivalent to an interrupt. This interrupt is caused by your eating, which is equivalent to an overflow of the flag in the system;
3. What are non-maskable interrupts and maskable interrupts?
Reference: CSDN blogger [lidandan2016] article: The difference between maskable interrupt and non-maskable interrupt
According to whether it can be masked , interrupts can be divided into two categories: non-maskable interrupt (also called non-maskable interrupt) and maskable interrupt.
Once a non-maskable interrupt source makes a request, the cpu must respond unconditionally , and for a request from a maskable interrupt source , the cpu can respond or not .
cup generally sets two interrupt request input lines: maskable interrupt request INTR (Interrupt Require) and non-maskable interrupt request NMI (Nonmaskable Interrupt). For maskable interrupts, in addition to being controlled by their own mask bits , they must also be controlled by a general control, that is , the interrupt enable flag bit IF (Interrupt Flag) in the CPU flag register. If the IF bit is 1, you can get the CPU Otherwise, no response will be obtained. Among them, the IF bit can be controlled by the user .
A typical example of a non-shielded interrupt source is a power failure . Once it occurs, it must respond immediately and unconditionally, otherwise it is meaningless to do any other work. A typical example of a maskable interrupt source is a printer interrupt . The CPU can respond to printer interrupt requests faster or slower, because it is entirely possible to let the printer wait for a while.
According to the above classification, there are 10 core interrupts and 82 maskable interrupts in STM32F4 , with 16 levels of programmable interrupt priority . As for what is the programmable interrupt priority , please read later.
2. How to configure the interrupt of STM32F4?
1. What is NVIC?
The full name of NVIC is Nested vectoredinterrupt controller, that is, nested vectored interrupt controller . For Cortex-M3 or M4 core MCUs, the priority of each interrupt is set with 8 bits in the register . With 8 bits, you can set 2 ^ 8 = 256 level interrupts. In practice, you can't use that much, so the chip manufacturer has made adjustments according to the chips they produce . For example, STM32F4 only uses the upper four bits [7:4] of the 8 bits, and the lower four bits take zeros, so that 2^4=16 , which can only represent 16 levels of interrupt nesting . For this NVIC, there is an important knowledge point that is priority grouping , preemption priority and response priority , the following will take STM32 as an example to introduce.
2. Priority grouping, preemption priority and response priority in NVIC
2.1 Preemption priority and response priority
First, a clear concept, if program A preemption priority is 0 , the program B preemption priority is 1 , the program A specific procedure B to seize the priority higher . That is, the smaller the number, the higher the priority .
Let's talk about preemption priority and response priority :
① : If program A is already in the implementation process, this time you want to start the implementation of the program B, then B if the preemption priority over A high , then B A can be interrupted , so that the system execution B.
② : If program A and program B want to start execution at the same time, and B's response priority is higher than A, the system executes B first.
2.2 Priority grouping
Priority can have five group numbers, namely 0 , 1 , 2 , 3 , 4. Different groups represent how many levels can be subdivided into preemption priority and response priority. For example, group 0 means 0:4 , that is 0 bit preempts priority, 4 bit response priority. In other words, for all interrupt programs in the system, the preemption priority is the same, all 0; and the response priority can have 2 ^ 4 = 16 different levels.
The following shows the specific distribution relationship table (from Punctual Atoms ):
When writing programs, we should first configure priority groups , and then configure the preemption priority and response priority of different interrupt programs.
3. How to configure STM32F4 interrupt in the program?
1. Configure priority grouping
In the program, priority grouping should be configured first, so that we can know how many levels of preemption priority and response priority are based on the grouping .
Configure priority grouping through the following functions :
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
Among them, since there are five different options for priority grouping: 0 , 1, 2, 3, and 4 , the parameters NVIC_PriorityGrouphave the following five options:
NVIC_PriorityGroup_0
NVIC_PriorityGroup_1
NVIC_PriorityGroup_2
NVIC_PriorityGroup_3
NVIC_PriorityGroup_4
2. Configure preemption priority and response priority
Configure the preemption priority and response priority through the following functions:
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
Among them, the parameter type NVIC_InitTypeDefis a structure, and its definition is as follows:
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
Among them, NVIC_IRQChanneldefine which interrupt is initialized. For this, we can find the corresponding name of each interrupt in stm32f10x.h. For example, USART1_IRQn ; NVIC_IRQChannelPreemptionPrioritydefine the preemption priority ofNVIC_IRQChannelSubPriority this interrupt ; define the sub-priority of this interrupt , also called response priority ; NVIC_IRQChannelCmdused to set the enable of the interrupt channel .
For example, we want to enable the interrupt of the serial port 1, and set the preemption priority to 1, and the response priority bit to 2. The initialization method is:
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;//串口 1 中断
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=1 ;// 抢占优先级为 1
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;// 响应优先级位 2
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //IRQ 通道使能
NVIC_Init(&NVIC_InitStructure); //根据上面指定的参数，调用函数来初始化 NVIC 寄存器，达到对中断进行设置的目的