Interrupt definition and its execution process
Interruption means that during the running of the main program, a specific interrupt trigger condition (interrupt source) occurs, causing the CPU to suspend the currently running program and turn to process the interrupt program. After the processing is completed, it returns to the original suspended position and continues to run. .
The STM32 microcontroller has 68 maskable interrupt channels (including EXTI, TIM, ADC, USART, SPI, I2C, RTC and other peripherals) and 16 programmable priority levels (using 4-bit interrupt priority).
Two words "maskable interrupt" and "priority level" need to be explained here.
According to whether it can be masked or not, interrupts are divided into two categories: non-maskable interrupts and frequency-blockable interrupts . A non-maskable interrupt means that once such an interrupt occurs, the CPU must respond unconditionally; a maskable interrupt means that after such an interrupt occurs, the CPU can respond to the interrupt or not.
The priority level refers to the order in which the CPU responds to interrupts. If two interrupts are triggered at the same time, the CPU will respond to the interrupts in order according to the priority level. First respond to the high priority level, and then respond to the low priority level . There may be a nested process. When an interrupt program is running, a new interrupt source with higher priority applies for an interrupt. The CPU suspends the current interrupt program again and turns to process the new interrupt program. After the processing is completed, it proceeds sequentially. return. The interrupt execution process is as follows.
Nested Vectored Interrupt Controller NVIC
The interrupt response and interrupt priority configuration of STM32 microcontrollers are controlled by NVIC. NVIC supports interrupt nesting, that is, interrupts with high priority can preempt low-priority interrupts, causing low-priority interrupts to hang. Suspend refers to suspension. Interrupts that are in progress are switched to higher-level or equivalent-level interrupts. For example, the first interrupt on the right side of the interrupt execution process diagram is suspended.
The structure of the NVIC is shown in the figure. All interrupts are processed by the NVIC before reaching the CPU. Which interrupt the CPU responds to first is determined by the NVIC. Therefore, if interrupts are used during program writing, the NVIC must be configured. Use NVIC to manage interrupts uniformly. Each interrupt channel has 16 programmable priority levels, which can be grouped to further set preemption priority and response priority.
As shown in the figure, STM32 has five interrupt priority assignment methods. Different grouping methods have different digits and value ranges of preemption priority and response priority. Those with high preemption priority can interrupt nesting, those with high response priority can be queued first, and those with the same preemption priority and response priority are queued according to the interrupt number. Simply put, those with high preemption priority can interrupt the interrupt response with low preemption priority, and the response priority under the same preemption priority is queued according to its priority, but the ongoing interrupt cannot be interrupted.
External Interrupt/Event Controller (EXTI)
EXTI is an external interrupt/event controller, which can monitor the level signal of the designated GPIO port. When the designated GPIO port has a level change, EXTI will immediately send an interrupt application to the NVIC, and the CPU main program can be interrupted after the NVIC judges , so that the CPU executes the interrupt program corresponding to EXTI.
Supported trigger methods : rising edge, falling edge, double edge and software trigger.
Supported GPIO ports : all GPIO ports, but the same Pin cannot trigger interrupts at the same time (because the corresponding interrupt lines are the same)
Trigger response mode : interrupt response/event response
EXTI supports all I/O trigger interrupts, but I/O There are many ports. If each I/O port uses an interrupt line, the number of interrupt lines will be large. Therefore, for easy management, STM32 adopts the method of I/O port and interrupt line mapping to reduce the number of interrupt lines. The number of broken lines.
As shown above, PA0, PB0, PC0...PG0 are all mapped to the EXTI0 interrupt line, PA1, PB1, PC1...PG1 are all mapped to the EXTI1 interrupt line, and subsequent images are deduced to EXTI15. Therefore, the same Pin cannot trigger interrupts at the same time, because one interrupt line can only be mapped to one port. For example, if PA0 has been used as the external interrupt input of EXTI0, then PB0, PC0...PG0 cannot be used as the external interrupt input of EXTI0. However, it should be noted that when programming, EXTI0~EXTI4 interrupt lines have their own independent input channels, but EXTI5~EXTI15 interrupt lines do not have their own independent channels , and the channels of EXTI5~EXTI9 are merged into EXTI9_5, EXTI10~ The EXTI15 channel is merged into EXTI15_10, and it is necessary to distinguish which interrupt line is interrupted by the flag bit.
The block diagram of the EXTI structure is shown in the figure. Starting from the lower right corner, the external interrupt signal reaches the edge detection circuit after passing through the input line. The edge detection circuit is controlled by the rising edge trigger selection register and the falling edge trigger selection register. Through the configuration of the corresponding bits of these two registers, the rising edge trigger, Falling edge trigger and double edge trigger. After the edge detection circuit is an OR gate, and the two inputs of the OR gate are the software interrupt event register signal and the edge detection circuit signal, that is, the edge trigger and event trigger in the EXTI trigger mode . After the OR gate, it is divided into two paths. Entering the request pending register upwards is to enter the interrupt response. If it is directly input to the AND gate, it is to enter the event response. These two paths are the interrupt response and event response in the EXTI trigger response mode. Which response mode to enter is controlled by the response bit of the request pending register and the event mask register. If it is an interrupt response, the signal comes out through the OR gate and then passes through the request suspension register and the corresponding bit of the interrupt mask register to allow it to reach the NVIC interrupt controller, which is processed by the NVIC and then handed over to the CPU for processing; The pulse generator is activated after the corresponding bit setting of the event mask register is enabled, and the pulse generator generates pulses to enable the corresponding built-in peripherals to work.
The APB bus in the upper part of the block diagram is connected to the peripheral interface, and then the peripheral interface is connected to each register, which means that the CPU can access each register through the APB bus and perform corresponding operations on the register.
From the EXTI structure diagram, we can see the EXTI trigger mode and trigger response.
Note: AFIO clock must be turned on when using external interrupt. AFIO clock is only used when using GPIO for EXTI external interrupt or when using remap function.
Summarize
Interruption is an important application of STM32. Clarifying the interrupt process and configuration method is more conducive to subsequent system learning.
The STM32 interrupt process can be roughly shown in the figure. Each interrupt source sends the interrupt signal to the NVIC for processing and then sends it to the CPU, and the CPU responds to each interrupt source.