2023 Software Test Intermediate "Software Designer" (Exam Preparation Sprint Version) | Computer Composition and Architecture

Table of contents

1. Basic computer knowledge

1.1 Representation of data

1.1.1 Base conversion (involving calculations)

 1.1.2 Code system (involving calculation)

1.1.3 Floating point number representation

1.1.4 Logical operations

1.2 Check code

1.2.1 Parity check code

1.2.2 CRC cyclic redundancy check code

1.2.3 Hamming check code (involving calculation)

2.Computer composition

2.1 Composition of CPU

2.2 Storage system

2.2.1 Hierarchical storage structure

2.2.2 Cache

2.2.3 Main memory addressing calculation (involving calculation)

2.3 Input and output technology

2.4 Bus technology

3. Command system

3.1 Addressing mode

3.2 CISC and RISC

3.3 Pipeline technology (involving calculations)

4.Reliability

5. Computer performance indicators


1. Basic computer knowledge

1.1 Representation of data

1.1.1 Base conversion (involving calculations)

Test points: Master the base conversion of data, binary, decimal, and hexadecimal conversion (basic knowledge for other questions)

Test method: Combined test with memory address calculation and IP address calculation

Key points:

        1. Convert decimal to R: short division

        2. Convert R base to decimal: weight expansion method

        3. Binary to octal, hexadecimal: fast conversion in groups

The beginning and end of the base
base beginning end
Binary 0b or 0B Ending with B
Octal Starting with 0 none
Decimal 0-9 none
Hexadecimal (Hex) 0x or 0X Ending with H
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1 2 4 8 16 32 64 128 256 512 102

 1.1.2 Code system (involving calculation)

Test points: Master the conversion rules of original code, inverse code, complement code, and frame code, and understand the range and number of representations of various code systems (note the artificial definitions of complement code and frame code)

Test method: Determine whether the description is correct; calculate the range of representation of a certain code system or the number of values ​​represented; the representation of different code systems

Key points:

1. The concepts of original code, complement code, complement code and frame code

coding system A positive number negative number
Original code The highest bit is the binary number with the sign bit, and the lower bit represents the absolute value of the value.
reverse code Same as original code It is the bitwise inversion of the low-order absolute value of the original code.
complement Same as original code It is the last digit of the complement code plus 1
frameshift The sign bit of the complement is bitwise inverted.

2. The representation range and number of representations of the code system

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  • The lower limits of complement and frameshift are considered to be prescribed. The artificially prescribed principle is not to treat the 1 in the sign bit as a negative sign, but to directly participate in the calculation, and a negative sign is added to the final result.
  •  In the original code and the complement code, +0 and -0 are repeated, so the number is reduced by 1; in the complement code and the frame code, the number -0 is used to participate in the artificial calculation, and finally becomes the lower limit of the range, so the number constant.

Question-solving skills:

        1. First check whether it is a fixed-point decimal or a fixed-point positive number;

        2. Uniformly convert into binary representation;

        3. Look at the code system and find the corresponding representation range;

        4. Calculate based on the relationship between code systems;

example:

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548eb9569cfe4c30a990f3c724ebb85b.jpeg

 

1.1.3 Floating point number representation

Test points: Master the format of floating point numbers and the meaning of each part, and understand the logical process of floating point number operations.

Test method: Determine whether the description is correct or incorrect, and determine the impact of digits and exponents on floating-point numbers.

Key points:

1. The meaning of each part of a floating point number: N = mantissa * base ^ order (the order is also called the exponent)

(1) Generally , the mantissa uses a complement code (fixed-point decimal) , and the exponent code uses a frame code (fixed-point integer) ;
(2) The number of digits in the exponent code determines the representation range of the number. The more digits, the larger the range ;

(3) The number of digits in the mantissa determines the effective precision of the number . The more digits, the higher the precision .

2. Floating-point number operation rules: Order alignment > Mantissa calculation > Result formatting
(1) When aligning the order , the decimal is aligned with the larger number ;
(2) The order alignment is achieved by shifting the mantissa of the smaller number to the right.

3. Number symbol : the sign bit of the mantissa ; order symbol : the sign bit of the order .

 

Question-solving skills:

        1. Find the code system corresponding to the mantissa and order respectively; (according to the question)

        2. If there are number symbols and order symbols, the number of mantissa digits and order digits is increased by 1; (the code system range takes the sign bit into consideration)

        3. Determine the representation range of floating point numbers according to the code system range;

example:

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 Disintegration ideas:

        1. Look at the exponent code (fixed-point integer, frame code representation gif.latex?-2%5E%7Bn-1%7D-+%282%5E%7Bn-1%7D-1%29): exponent symbol + exponent code, n=1+6=7 ; the exponent code range is -64-63

        2. Look at the mantissa (fixed-point decimal, complement representation gif.latex?-1-+%281-2%5E%7B-%28n-1%29%7D%29): number symbol + digit, n=1+8=9;

        3. Combine the options to see if there is a range that includes repeated parts. You can combine the coordinate axis drawing to select a larger range;

1.1.4 Logical operations

Test points: Priority of arithmetic and logical operations, short-circuit principle

Test method: Give calculation results or equivalent expressions based on operational expressions; judge the short-circuit principle;

Key points:

1. Operator:
Higher priority (relational operator): <
(less than); <= (less than or equal to); > (greater than); >= (greater than
or equal to).
Lower precedence (relational operators): = equals; ! = not equal.
Logical operators:
Logical OR (, +, U, V, OR):
0 is taken only when the two connected logical values ​​are all 0 .
Logical AND (&&, *, ·, ∩, eight, AND): 1 is taken only when
the two connected logical values ​​are all 1. Logical exclusive OR (⊕ ,
Logical negation (!, one, ~, NOT,):
Just invert the original logical value .


2. Prioritize
!
"&&" and "||" in the (not), && (and), | (or) logical operators are lower than the relational operators, and "!" is higher than the arithmetic operators.
Therefore the order of precedence of operators is: ! >Arithmetic operators>Relational operators>&&>||>Assignment operators.


3. Short-circuit principle: In the solution of logical expressions, not all logical operators must be executed.

(1) a&&b&&c Only when a is true, the value of b needs to be judged. Only when a and b are both true,
the value of c needs to be judged.
(2) a||b||c As long as a is true, there is no need to judge the values ​​of b and c. Only when a is false, b can be judged.
C is judged only when both a and b are false.

1.2 Check code

Test points: Understand parity check, understand CRC check (calculated using modulo-two division), master Hamming check digit calculation, and distinguish the error detection and correction characteristics of the three check methods.

Test method: Judgment of various check codes; calculation of Hamming check codes

Key points:

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1. Check code concept: adding certain redundant information to the original information to help with verification

2. Code distance: The least changed binary digits between any two code words is called the code distance of the data check code.

The code distance between the group of 4 code words {00, 01, 10, 11} is 1, for example {00 to 01}; and the code distance of {00 to 11} is 2, which is larger than 1, so the minimum value must be selected. .

1.2.1 Parity check code

Information bit + check bit (1 bit)

Check odd (even) data bit numbers, not odd (even) bits.

The error of 1 data bit can be checked and cannot be corrected.

1.2.2 CRC cyclic redundancy check code

Information bit + check bit (no longer 1 bit), the number of bits is determined by the generator polynomial, and according to the modulo two division, the number of bits corresponds to the remainder.

Error detectable but not correctable

Note: CRC check details are only for advanced candidates.

1.2.3 Hamming check code (involving calculation)

Important formula:gif.latex?2%5E%7Br%7D%5Cgeqslant%20m&plus;r&plus;1

Among them: m is the length of the information bits, r is the required check digit length (that is, how many check digits)

Question-solving skills:

        1. When calculating r based on m, select m gif.latex?2%5E%7Bn%7D closer to the top, for example, m=50, between gif.latex?2%5E%7B5%7Dand gif.latex?2%5E%7B6%7D ;

        2. And because m is already greater than gif.latex?2%5E%7B5%7D+r+1 is added after the inequality, it gif.latex?2%5E%7Br%7D must be greater than or equal to 6;

        3. Therefore, the order of the upper limit of m is generally directly selected as r.

 4. The check digit is         placed in a position up to  gif.latex?2%5E%7B0%7D.gif.latex?2%5E%7B1%7Dgif.latex?2%5E%7Br%7D

2.Computer composition

2.1 Composition of CPU

Test points: Master the functions and classification of each sub-component of the CPU

Test method: Given a component, determine whether it belongs to an arithmetic unit or a logic device. Given a functional description, determine what component it is.

Key points:

operator Arithmetic Logic Unit ALU Arithmetic and logical operations on data
Accumulation register AC General-purpose registers provide a work area for the ALU and are used to temporarily store data
Data buffer register DR When writing to memory, instructions or data are temporarily stored
Status condition register PSW Storage status flags and control flags (controversy: some also classify them as controllers)
 

 

 

 

controller


 

Program CounterPC Store the address of the next instruction to be executed
Instruction register IR Store instructions to be executed
Instruction decoder ID Analyze and interpret the opcode field in the instruction
sequential components Provide timing control signals

2.2 Storage system

2.2.1 Hierarchical storage structure

 

Test points: Understand the concepts related to computer hierarchical storage structure (efficiency, capacity, cost comparison, locality principle)

Test method:

Key points:

1. Hierarchical hierarchical storage structure

Hierarchical hierarchical storage structure: 4 layers--CPU, Cache, memory (main memory), external memory (auxiliary memory)

Three-level storage system: 3 layers--Cache, memory, external storage

Virtual storage system: 2--memory, external storage

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 2. Classification of hierarchical storage structures64737e27cad747a39b38730dea5de15e.jpeg

 3. The principle of locality

Temporal locality: The content that was just accessed is accessed again immediately (loop structure)

Spatial locality: the content that has just been accessed, the adjacent space will be accessed soon (sequential structure)

2.2.2 Cache

 

Test points: Understand the principle of locality, be familiar with the related concepts and characteristics of Cache, and distinguish the three mapping methods of Cache

Test method: multiple choice questions, comparison and differentiation of Cache mapping methods; the control of Cache mapping methods is directly controlled by the hardware (frequent test)

Key points:

1. Cache related concepts: theoretical basis (principle of locality), comparison of size, speed, cost, etc.

In the computer storage system, Cache is the fastest access level (except registers). Cache improves system performance and increases the efficiency of CPU access to memory.


Cache's address mapping is completed directly by the hardware. (frequent exam)


2. Cache mapping methods: Comparison of fully associative, set associative, and direct associative images (the conflict rate increases in order, and the circuit complexity decreases in order)

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2.2.3 Main memory addressing calculation (involving calculation)

Test points: Master the main memory computing model and master the calculation of relevant parameters (number of storage units, total storage capacity, unit chip capacity, number of chips)

Test method: Calculation questions, total memory capacity, chip unit capacity, number of chips

Key points:

1. Number of storage units: maximum address + 1 - minimum address

2. Total memory capacity: byte addressing: number of memory units * 8 bit (1 byte B = 8 bit); word addressing, number of memory units * machine word length

3. Total number of slices = total capacity/capacity of each slice

4. Chip unit capacity = total capacity/number of chips

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 Question-solving skills:

        1. Pay attention to memory size conversion

        2. Unify the unit

2.3 Input and output technology

Test points: interrupt; DMA

Test method: Interrupts and DMA are inspected more frequently

Key points:

1. Data transmission control method

Program control (query) mode It is divided into two types: unconditional transmission and program query.
The method is simple and has low hardware overhead, but the I/O capability is not high, which seriously affects the CPU utilization.
Program interrupt mode

Compared with the program control method, the interrupt method improves the response speed of transmission requests (mouse and keyboard) because the CPU does not need to wait.

(Interrupt vector table: saves the entry address of the interrupt service routine)

DMA mode         The DMA method is set up to achieve high-speed, batch data exchange between main memory and peripherals . DMA mode is more efficient than program control mode and interrupt mode . (DMAC makes a bus request to the bus arbitration logic; the CPU can release the bus control right after executing the current bus cycle . At this time, the DMA responds and notifies the I/O interface through the DMAC to start DMA transmission.) (The CPU is not required to participate in data transmission)

2.4 Bus technology

Test points: Understand bus classification, data bus, control bus, address bus;

Test method: Determine the bus classification

Key points:

1.Bus classification

Data Bus (DB, Data Bus)
Data that needs to be processed or needs to be stored is transferred back and forth between the CPU and RAM .
地址总线(AB,Address Bus) 用来指定在RAM(Random Access
Memory)之中储存的数据的地址
控制总线(CB,Control Bus) 将微处理器控制单元(Control Unit)
的信号,传送到周边设备。

3.指令系统

考点:了解指令的基本分类,、寻址方式分类

考法:根据CISC和RISC的特点判断对错;根据描述回答是哪种寻址方式

3.1 寻址方式

要点:

 

寻址方式 特点
立即寻址方式 操作数直接在指令中,速度快,灵活性差
直接寻址方式 指令中存放的是操作数的地址
间接寻址方式 指令中存放了一个地址,这个地址对应的内容是操作数的地址。
寄存器寻址方式 寄存器存放操作数
寄存器间接寻址方式 寄存器内存放的是操作数的地址

3.2 CISC和RISC

要点:

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3.3 流水线技术(涉及计算)

考点:掌握流水线相关参数计算,

考法:相关概念和相关计算

要点:

        1.流水线相关概念:针对多条指令执行效率说的;

        2.流水线建立时间:一条指令执行时间(取指+分析+执行);

        3.流水线周期:执行时间中最长的一段;

        4.流水线执行时间(理论公式):gif.latex?t_%7B1%7D&plus;t_%7B2%7D&plus;...&plus;t_%7Bk%7D&plus;%28n-1%29*t 

一条指令执行时间+(指令条数-1)*流水线周期

        5.流水线执行时间(实践公式):理论算出来没有正确答案时考虑

gif.latex?k*t&plus;%28n-1%29*t,其中k是划分的段数,(取指+分析+执行,k=3),t是流水线周期

        6.流水线吞吐率:TP=指令条数/流水线执行时间,(本质还是考理论公式)

        7.流水线最大吞吐率:流水线周期倒数gif.latex?%5Cfrac%7B1%7D%7Bt%7D

        8.流水线加速比:不使用流水线加速时间/使用流水线加速时间

4.可靠性

考点:掌握系统可靠性计算(串联系统、并联系统、混联系统)

考法:不同系统类型的可靠性计算

要点:

1.可靠性指标计算

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2.串联系统、并联系统、混联系统

串联系统计算 R总=R1*R2*..*Rn;
并联系统计算 R总=1-(1-R1)(1-R2)..(1-Rn);
N模混联系统 First divide the entire system into multiple parts connected in series with R1, R2, etc., then calculate R1 and the internal parallel reliability and bring them into the original formula

5. Computer performance indicators

Test point: Understand common computer performance indicators

Test method: Give a description, determine the corresponding performance indicators; calculate the performance indicator parameters

Key points:

System performance index parameters
word length The length of data that the computer can read at one time: 32 bits
data path width The amount of data that a one-time data (data pulse) line can pass through
Main memory capacity and access speed 8G,16G
Main frequency The number of times data can pass through in 1 second
CPU clock cycle The reciprocal of the main frequency
CPI Average number of clock cycles per instruction (CPI, clock per instruction) C/I
IPC The number of instructions running per (clock) cycle (IPC, instruction per clock) I/C, and CPI are the reciprocal of each other
MIPS

Million instructions per second (Million Instruction per Second)

MIPS=number of instructions/(execution time*10^6)=main frequency/CPI=main frequency*IPC

MFLOPS

millon floating-point operations per second

MFLOPS=number of floating point operations/(execution time*10^6)

Response time RT The time from submitting a request to completing the request (respponse time)
Completion time TAT Instruction execution completion time
Throughput The amount of tasks completed within a certain time interval
Throughput Throughput per unit time
compatibility When installing

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Origin blog.csdn.net/qq_35902025/article/details/130193646