In zynq series, PS and PL data exchange primarily through AXI bus for transmitting small amounts of data (e.g., configuration registers, status information acquisition, etc.) often adopt AXI4-LITE. For large, high-speed data transmission, often used AXI4-FULL. Although the official, there are many templates, but the principle of "self-sufficiency", combined with "for them is the best" approach, to determine their own design a Slave AXI4 Lite interface.
Design goals:
CPU exchanges data through AXI4-Lite interface FPGA. Configuration registers and is mainly read.
designing process:
Since the register is determined by the address, therefore, we need to be converted into a form AXI4 RAM interface protocol, i.e., write enable, write address, write data, read enable, six read port address, read data and the like. Because they do not have burst capability, therefore, each read (write) requests a read only (write) data is generated.
method one:
Custom template, select AXI4-Lite, Slave mode upon generation Vivado, any other parameters. After the template generation, added wren, wraddr, wrdata, rden, rdaddr, rddata six ports, while the can, in order to improve the timing of reading, the read valid signal may be done on a 1 to access the interface bus template axi N cycles delay. In this design, I would wren, wraddr, wrdata registration process were carried out, but also will rden, rdaddr were registered, at last, turn rddata setting is valid for the two clock cycles after rden. So, even if a large timing tense situation at the back end of the fan, it will not cause timing problems. The rdata delayed by 2 clock cycles, because the axi-lite addition to reading large number of registers, RAM or FIFO will read a plurality of such second beat delay can also register rebalance (integrated tools or artificially designed implementation) optimize the structure timing mode.
Method Two:
Designing with HLS, the input designated as s_axilite. After synthesis, the internal ram is removed, while the RAM interface can lead, in order to improve the timing of reading, the read valid signal can be delayed 1 ~ N cycles. HLS processing interface is very flexible, especially in terms of the definition of IP, but in this design, I have not found a way to directly generate the target function, you need to do some cropping of the code generation.
postscript:
In this design, two design methods complexity is roughly equal, although HLS has been able to do a lot of design, but there are many shortcomings comprehensive understanding of HLS, follow the detailed study to do. HLS will have time to finish uploading functions are done to make learning backup.