AXI4-Stream protocol summary and analysis

First, the agreement introduces

. 1, AXI4_Stream : for high-speed data streams, remove the address entry, allowing unlimited data burst transmission. In addition to the bus and clock bus reset, other interface signals begin with the letter T.

2, signal interface description:

(1), ACLK --------- ----- global clock source clock signal, all the signal samples at the rising edge of the master clock signal.

(2), ARESETN ------ ------ active low reset.

(3), Tvalid ------- host data valid signal (difference AXI4, AXI4-Lite, AXI4_Stream remove the address entry), issued by the host, high-speed data sent from the machine effectively. Source for the master.

(4), Tdata [31: 0] - Data sent by the host, an optional data width, 32/64/1278/256 bit. Source bit master.

(5), Tkeep [3: 0] --- modifier byte for indicating the contents associated Tdata is a valid byte of data, the bit is not acknowledged Tkeep Kong Zijie byte, byte deemed irrelevant, It may be removed from the byte stream. Source for the master.

(6), Tlast -------- notifies the host machine from the last time data, i.e. the data packet boundary. Source for the master.

(7), Tid --------- issued by the host, Identity identifier, when a plurality of data stream transmission function, for identifying the different data streams. Source for the master.

(8), Tready ------ emitted from receives ready signal.

Second, the communication mechanism

  The most important thing to keep in mind that only  1 Tvalid & Tready ==  can begin data transmission time, Valid signal is generated by the data transmission source, Ready signal generated by the destination source (from the United meters off the book, these words sum up too classic, because at other AXI4 bus when data reading, the host will produce Rready signal).

   Because AXI4-stream to remove the address lines (data flow identification relies Tid), do not involve the communication of data reading and writing, involves only a simple transmission and reception, transmission delay is reduced.

Third, exemplified

 

  REG [ 31 is : 0 ] S_AXIS_tdata; // send data 
  REG   S_AXIS_tlast;   // end of burst transfer 
  REG S_AXIS_tvalid;   // The effective transmission 
  Wire FCLK_CLK0; // transmit clock 
  Wire s_axis_aclk;
   Wire s_axis_aresetn;
   Wire [ . 3 : 0 ] S_AXIS_tkeep; // . 4 th byte are valid 
  Wire S_AXIS_tready; // receiving a ready signal from the slave 
  Wire [ 0 : 0 ] gpio_rtl_tri_o;
   Wire [ 0 :0]peripheral_aresetn;
  reg [1:0] state;//状态机
  
assign S_AXIS_tkeep = 4'b1111;  
assign s_axis_aclk =  FCLK_CLK0;
assign s_axis_aresetn = peripheral_aresetn;
  
always@(posedge FCLK_CLK0)
   begin
       if(!peripheral_aresetn) begin
           S_AXIS_tvalid <= 1'b0;
           S_AXIS_tdata <= 32'd0;
           S_AXIS_tlast <= 1'B0; 
           State <= 0 ;
        End 
       the else  the begin 
          Case (State)
             0 : the begin    // wait to allow transmission and reception ready signal since the incoming 
                IF (gpio_rtl_tri_o && S_AXIS_tready) the begin 
                   S_AXIS_tvalid <= . 1 ' B1; // host the valid position PL a 
                   State <= . 1 ;
                 End 
                the else  the begin 
                   S_AXIS_tvalid <= . 1 ' B0; 
                   State <= 0 ;
                 End 
              End
            . 1 : the begin     // if the slave is ready to start data transmission 
                 IF (S_AXIS_tready) the begin 
                     S_AXIS_tdata <+ = S_AXIS_tdata . 1 ' B1; 
                     IF (S_AXIS_tdata == 16 ' is set after d510) begin // End of transmission data last 511 signal 
                        S_AXIS_tlast <= . 1 ' B1; 
                        State <= 2 ;
                      End 
                     the else  the begin 
                        S_AXIS_tlast <= . 1 ' B0; 
                        State <= . 1 ;
                     End 
                 End 
                 the else  the begin 
                    S_AXIS_tdata <= S_AXIS_tdata;                    
                    State <= . 1 ;
                  End 
              End        
            2 : the begin   // Wait been received from the machine, a vessel in preparation for transfer 
                 IF (S_AXIS_tready!) the begin 
                    S_AXIS_tvalid <= . 1 ' B1; 
                    S_AXIS_tlast <= . 1 ' B1; 
                    S_AXIS_tdata <= S_AXIS_tdata; 
                    State <= 2 ;
                  End
                 else begin
                    S_AXIS_tvalid <= 1'b0;
                    S_AXIS_tlast <= 1'b0;
                    S_AXIS_tdata <= 32'd0;
                    state <= 0;
                 end
              end
           default: state <=0;
           endcase
       end              
   end