1. AXI4 channel
read address channel (Read address channel, AR)
write address channel (Write address channel, AW)
read data channel (Read data channel, R)
write data channel (Write data channel, W)
to write response channel (Write response channel, B)
each consist of one channel, and uses bidirectional VALID handshake signal and the READY mechanism.
2. Assignment AXI4 
3. write waveform AXI4
AXI4 burst write waveform, as shown below. 
AXI4 read burst waveform, as shown in FIG. 
AXI4-Lite 4.
AXI4-Lite interface is a subset AXI4 interface, small size, has the following characteristics:
- All transactions burst length is 1
- All access to the data the same width
- Only supports 32-bit or 64-bit access
- All access AWCACHE and ARCACHE equal to 0
- It does not support mutual exclusion