Detailed explanation of DDR hardware design points (including power supply)

Reprinted from  http://www.fairchildic.org/module/forum/thread-658-1-1.html  (the original post includes detailed attachments)


1. The power supply of the power supply DDR can be divided into three categories
A. The main power supply VDD and VDDQ, the main power requirement is VDDQ=VDD, VDDQ is the power supply for the IO buffer, VDD is for the power supply, but in general use, VDDQ and VDD are combined into one power supply.
Some chips also have VDDL, which supplies power to the DLL, and can also use the same power supply as VDD. When designing a power supply, it is necessary to consider whether the voltage and current meet the requirements, the power-on sequence of the power supply, the power-on time of the power supply, and monotonicity. The power supply voltage requirement is generally within ±5%. The current needs to be calculated according to the different chips used and the number of chips. Since the current of DDR is generally relatively large, it is the most ideal state if a complete power plane is laid on the pins during PCB design, and the capacitor energy storage is increased at the power inlet, and one is added to each pin. 100nF~10nF small capacitor filter.

B. The reference power supply Vref, the reference power supply Vref is required to follow VDDQ, and Vref=VDDQ/2, so it can be provided by a power supply chip, or it can be obtained by means of a resistor divider. Since the current of Vref is generally small, in the order of several mA to tens of mA, the resistor divider method is used, which saves costs and is more flexible in layout. It is placed close to the Vref pin and closely follows. VDDQ voltage, so this method is recommended. It should be noted that the resistor used for voltage division can be 100~10K, and a resistor with 1% accuracy needs to be used. A 10nF point capacitance filter needs to be added to each pin of the Vref reference voltage, and it is better to connect a capacitor in parallel with each voltage dividing resistor.

C. Voltage VTT (Tracking Termination Voltage) for matching
VTT is the power supply pulled up by the matching resistor, VTT=VDDQ/2. In the design of DDR, depending on the topology, some designs do not use VTT, such as when the controller has fewer DDR devices. If VTT is used, the current requirement of VTT is relatively large, so the traces need to be laid with copper. And VTT requires that the power supply can both sink current and sink current. Under normal circumstances, a power supply chip specially designed for DDR to generate VTT can be used to meet the requirements.
Moreover, a 10Nf~100nF capacitor is generally placed next to each resistor pulled to the VTT, and a large uF capacitor is required for energy storage on the entire VTT circuit.
In Huawei's design, in the case of using DDR chips, the VTT power supply is basically not used.

Under normal circumstances, DDR data lines are of a one-drive-one topology, and both DDR2 and DDR3 have ODT for matching, so they do not need to be pulled to VTT for matching to obtain better signal quality. If the address and control signal lines of DDR2 are multi-loaded, there will be more than one drive, and there is no ODT inside, and its topology is a T-shaped structure, so VTT is often used for signal quality matching control. DDR3 can use Fly-by routing:
a DDR3 design case to analyze and compare the difference between using high impedance load routing and using the same impedance of main and load routing.


As shown in the figure above, Case1 adopts an impedance design of 50ohm from the inner controller to each SDRAM. Case2 adopts the design of 40ohm main line and 60ohm load line. This is compared and analyzed through simulation tools.


As can be seen from the above simulation waveforms, Case2 using higher impedance load traces is significantly better than Case1 design using the same impedance for both branch and main lines in terms of signal quality. Moreover, the load close to the drive end has the greatest impact, and the load at the extreme end far from the drive end has less impact. This is exactly what has been analyzed before. The distributed capacitance of the load causes the impedance of the load line to decrease. If the main line and the load line are designed with the same impedance, it will lead to the occurrence of impedance discontinuity. The load trace is designed to have a higher impedance to balance the distributed capacitance introduced by the load, so that the impedance balance of the entire trace can be achieved.
The practice of balancing the load capacitance by increasing the load trace impedance is actually a method often used in the previous daisy-chain design. DDR3 calls this topology fly-by, which actually has a certain meaning, which is intended to emphasize that the load stub trace is short enough.

2. The clock
of the clock DDR is a differential line. Generally, the terminal is connected in parallel with a 100-ohm matching method. The differential pair control impedance of the differential line is 100ohm, and the single-ended line is 50ohm. It should be noted that series matching can also be used for differential lines. The advantage of using series matching is that the rising edge slowness of the differential signal can be controlled, which may have a certain effect on EMI.

3. Data and DQS
The DQS signal is equivalent to the reference clock of the data signal, and it needs to be maintained for the same length as the CLK signal when routing. DQS is a single-ended signal below DDR2. DDR2 can be used as a differential signal or single-ended. When single-ended, DQS- needs to be grounded, while DDR3 is a differential signal and needs to be routed with a 100ohm differential line. Since there is an ODT inside, the DQS does not require a 100ohm resistor in parallel with the terminals. Each 8bit data signal corresponds to a group of DQS signals.
The DQS signal needs to keep the same length as the DQS signal of the same group when routing, and control the single-ended 50ohm impedance. When writing data, the middle of DQ and DQS are aligned, and when reading data, the edges of DQ and DQS are aligned. Most of the DQ signals are one-drive-one, and DDR2 and DDR3 have internal ODT matching, so it is generally enough to perform series matching.

4. Address and Control

The speed of the address and control signals is not as fast as that of the DQ, and they are sampled based on the rising edge of the clock, so they need to be kept the same length as the clock traces. However, when using multiple DDR chips, the address and control signals are in a one-drive-many relationship, so you need to pay attention to whether the matching method is suitable.

5. Precautions for PCB Layout During
PCB layout, the DDR particles need to be placed as close to the DDR controller as possible. A filter capacitor needs to be placed on each power pin, and a large capacitor of more than 10uF needs to be placed on the power inlet on the entire power supply. The power supply is best applied to the pins using a separate layer. The resistors matched in series are best placed at the source end. If it is a bidirectional signal, they should be placed at the same end. If it is a multi-drive DDR matching structure, the VTT pull-up resistor needs to be placed at the farthest end, and the arrangement of the chip needs to be balanced. The figure below shows the topological structures of several DDRs. First, in the case of one-drive-two, it is divided into tree structure, daisy-chain and Fly-by structure. Fly-by is a daisy-chain structure with a small STUB. DDR2 and DDR3 are more suitable for daisy-chain structure. The tree structure can be used to stick two chips on the front and back sides of the PCB, and the length of the bifurcation can be reduced. One-drive-multiple DDR topologies are complex and require careful simulation.

6. Precautions for
PCB wiring When wiring the PCB, the single-ended wiring should be 50ohm, and the differential wiring should be 100ohm impedance.

Note that the equal length of the differential line is within ±10mil. The same group of traces has different speed requirements, generally ±50mil.

The control and address lines and the DQS lines are the same length as the clock, and the DQ data lines are the same length as the DQS lines in the same group.

Note that the clock, DQS and other signals should be separated by more than 3W.

The signals between groups should also be separated by a distance of at least 3W.

The same group of signals is best routed on the same layer.

Minimize the number of vias.

7. EMI problem
Because DDR has high speed and frequent access, its external interference needs to be considered in many designs, and the following points need to be paid attention to when designing

The principle requires performance indicators, and easily interfered circuit modules and signals, such as analog signals, radio frequency signals, clock signals, etc., prevent DDR from interfering with them and affecting indicators.

Do not use the same power supply for the DDR power supply and other power modules that are susceptible to interference. If the same power supply must be used, pay attention to using inductors, magnetic beads or capacitors for filtering and isolation.

On the clock and DQS signal lines, reserve some positions for series resistance and parallel capacitance that can be added. When the EMI exceeds the standard, increase the series resistance or ground capacitance within the range allowed by signal integrity to make the signal rise and delay. slow down and reduce external radiation.

Shielding treatment is carried out, and the shielding structure of the metal shell is used to shield the external radiation.
Take care to maintain the integrity of the ground.

7. EMI problem
DDR due to its fast speed and frequent access, so it needs to consider its external interference in many designs. In the design, you need to pay attention to the following

principles. There are performance indicators, circuit modules and signals that are susceptible to interference, Such as analog signals, RF signals, clock signals, etc., to prevent DDR from interfering with them and affecting indicators.

Do not use the same power supply for the DDR power supply and other power modules that are susceptible to interference. If the same power supply must be used, pay attention to using inductors, magnetic beads or capacitors for filtering and isolation.

On the clock and DQS signal lines, reserve some positions for series resistance and parallel capacitance that can be added. When the EMI exceeds the standard, increase the series resistance or ground capacitance within the range allowed by signal integrity to make the signal rise and delay. slow down and reduce external radiation.

Shielding treatment is carried out, and the shielding structure of the metal shell is used to shield the external radiation.

Take care to maintain the integrity of the ground.