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1. Introduction
There is only one 50MHz clock input on the ZYNQ development board. If you want to use clocks of other frequencies, you need to divide or multiply the frequency through the PLL (Phase Locked Loop) integrated inside the FPGA chip.
A complex system often requires multiple clock signals of different frequencies and different phases, so the number of PLLs in the FPGA chip is also an important indicator of measuring the performance of the FPGA chip. In the design of FPGA, the high-speed design of the FPGA clock system is very important. A low-jitter, low-latency system clock will increase the success rate of FPGA design.
This experiment achieves frequency division and multiplication by adding a clock IP core.
2. Add clock IP
Open the IP Catalog, search for Clocking, find the Clocking Wizard, and double-click to open it.
After opening, the following dialog box will pop up, select PLL, and set the input clock to 50MHz.
MMCM (Mixed Mode Clock Manager) is a mixed mode clock manager used to generate different clock signals with a set phase and frequency relationship with a given input clock.
PLL is mainly used for frequency synthesis. Using one PLL can generate multiple clock signals from one input clock signal.
Then set four output frequencies under the output clock subpage.
After the settings are completed, click OK and the following window will pop up. Click Generate to complete the addition of the clock IP core.
3. Design source code
Under IP Sources, find the .veo file that added the clock IP core above, and double-click to open it as shown below.
Copy the instantiation code, create a new design source file, and paste it into it. The final code is as follows.
module pll(
input clk,
input rst,
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4
);
wire locked;
clk_wiz_0 clk_wiz_0_inst
(
// Clock out ports
.clk_out1(clk_out1), // output 200MHz
.clk_out2(clk_out2), // output 100MHz
.clk_out3(clk_out3), // output 50MHz
.clk_out4(clk_out4), // output 25MHz
// Status and control signals
.reset(~rst), // input reset
.locked(locked), // output locked
// Clock in ports
.clk_in1(clk)); // input 50MHz
endmodule
It should be noted here that the reset of the PLL is active at a high level. If it is later required to reset by pressing a button on the development board, since the button is active at a low level, the reset signal in the above code needs to be reversed.
4. Simulation test
The simulation test source code in this example is as follows.
`timescale 1ns / 1ps
module sim_pll();
reg clk;
reg rst;
wire clk_out1;
wire clk_out2;
wire clk_out3;
wire clk_out4;
initial
begin
clk = 0;
rst = 1; //PLL复位高电平有效，代码中有取反，所以这里设置为1
end
always #10 clk = ~clk;
pll uut_pll(
.clk(clk),
.rst(rst),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
.clk_out4(clk_out4)
);
endmodule
The simulation output results are shown in the figure below.
The clock in the code has a cycle of 20ns, so the frequency is 50MHz. From the above output results, we can see that the frequency of clk_out1 is 4 times the input clock frequency, which is 200MHz. Similarly, the frequency of clk_out2 is 2 times the input clock frequency, which is 100MHz. clk_out3 has the same frequency as the input, which is 50MHz. The frequency of clk_out4 is 0.5 times the input clock frequency, which is 25MHz.
Change the phases of clock 3 and clock 4 in the PLL, as shown below.
The simulation output result after modifying the phase is shown in the figure below.
Comparing it with the above when the phase has not changed, it can be clearly seen that clock 3 and the input clock are in opposite directions, that is, the phase shift is 180°, and clock 4 has a phase shift of 90° compared to the input clock.
Therefore, through the above simulation, it can be found that multiple clock signals of different frequencies and different phases can be generated through the PLL.
5. Add ILA IP
Five probes are added here, all one-bit, for observing the output signal.
6. Assign pins
When using the above code to verify on the board, an oscilloscope is required to measure it. Here I analyze the output results by adding ILA, and the code I wrote is as follows.
module pll(
input clk,
input rst,
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4
);
reg in,out1,out2,out3,out4;
wire locked;
initial
begin
in = 1;
out1 = 1;
out2 = 1;
out3 = 1;
out4 = 1;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
in = 0;
else
in = ~in;
end
clk_wiz_0 clk_wiz_0_inst
(
// Clock out ports
.clk_out1(clk_out1), // output 200MHz
.clk_out2(clk_out2), // output 100MHz
.clk_out3(clk_out3), // output 50MHz
.clk_out4(clk_out4), // output 25MHz
// Status and control signals
.reset(~rst), // input reset
.locked(locked), // output locked
// Clock in ports
.clk_in1(clk)); // input 50MHz
always@(posedge clk_out1)
begin
if(!rst)
out1 = 0;
else
out1 = ~out1;
end
always@(posedge clk_out2)
begin
if(!rst)
out2 = 0;
else
out2 = ~out2;
end
always@(posedge clk_out3)
begin
if(!rst)
out3 = 0;
else
out3 = ~out3;
end
always@(posedge clk_out4)
begin
if(!rst)
out4 = 0;
else
out4 = ~out4;
end
ila_0 ila_inst (
.clk(clk),
.probe0(in),
.probe1(out1),
.probe2(out2),
.probe3(out3),
.probe4(out4)
);
endmodule
Assign pins to each port in the code as shown below.
7. On-board verification
Generate the bitstream and download it to the ZYNQ development board for verification.
View the output results in the integrated logic analyzer window as shown below.
The picture above is when the input is 50MHz, and out1 (200MHz) and out2 (100MHz) are not displayed correctly.
According to what is written in the code, the in signal represents the input clock (the in signal is divided by two of the actual clock frequency, but it does not affect the comparison with subsequent frequencies, because the output signals are all generated under this mechanism, so the multiple relationship does not matter. will change), I changed it to 200MHz, because when 50MHz was verified on the board, I found that the two frequencies of the multiplier output, 100MHz and 200MHz, could not be output correctly, but the frequency division could be output normally, so I changed it to 200MHz. Just watch The result of frequency division.
It can be seen that the output out1 has the same frequency as the input in signal; the output out2 is the frequency divided by two of the input in signal; the output out3 is the frequency divided by four of the input in signal; and the output out4 is the frequency divided by eight of the input in signal. This is consistent with what I preset in the PLL, but if you look closely at the two figures above, you will find that when the input is 50MHz and 200MHz, the waveform of the in signal is consistent, so it is not accurate to view the output through ILA.
8. Oscilloscope output
I originally wanted to verify the output results through ILA, but a series of problems arose, so I decided to measure the frequency of the relevant pins in an oscilloscope.
The input is still set to 50MHz, and the output clock is set as follows.
Generate a bitstream file in Vivado, download it to the development board, and then measure the frequency of the relevant pin according to the pin assignment.
The output of the 200MHz pin in the oscilloscope is shown below.
The output of the 100MHz pin in the oscilloscope is shown below.
The output of the 50MHz pin in the oscilloscope is shown below.
The output of the 25MHz pin in the oscilloscope is shown below.
It can be seen from the results of the above figures that the frequency can be output as set in the code. However, the output waveform does not look like a square wave, but more like a sine wave. This is because the bandwidth of the oscilloscope is not enough. You can refer to the article about the bandwidth of the oscilloscope. Generally, when the bandwidth of the oscilloscope is 5 times the frequency of the measured signal, the square wave will be more obvious. , in the above four pictures, as the frequency decreases, the waveform becomes closer to a sine wave. But the waveform is not the focus of our concern here, the frequency output is correct.
9. Summary of issues
This experiment went smoothly during the simulation process and basically encountered no problems. However, we encountered some troubles when verifying on the board, which are listed below.
1. An error occurred when running, as shown in the figure below.
The error message is as follows.
[DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal clk_wiz_0_inst/inst/clk_in1 on the clk_wiz_0_inst/inst/plle2_adv_inst/CLKIN1 pin of clk_wiz_0_inst/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
Solution: Go back to the PLL IP core and change the Source to Global buffer.
2. The input clock frequency cannot be viewed directly through the probe. The output is a line. Therefore, I introduced the reg variable in the code and inverted the value on the rising edge of the clock to represent the frequency. The actual frequency should be this representation. The method is expressed as twice the value, but this is just to verify the relationship between each output frequency and the input frequency. Therefore, this difference does not affect the final result determination.
3. When verifying on the board, I found that the frequency multiplication waveform output was incorrect but the frequency division was correct. I don’t know what caused it. I directly changed the input frequency to the maximum here and only verified the correctness of the frequency division.
4. There is another problem that is not a problem. It is a simple operation. The default pin assignment window is opened as shown in the figure below.
You can see that the Name column is empty. When assigning pins, which port in the code the port corresponds to can be known through the I/O Ports Properties, but I always feel that something is not quite right. Yes, something is indeed wrong. Use the mouse to pull the column corresponding to Name wider and you will find the "New World"!
The above is the entire content of the ZYNQ-Phase Locked Loop (PLL) experiment. I always encounter strange problems of this kind in the experiment. Although the process of discovering problems and finding solutions is a bit painful and even a bit desperate, these They are all the way to go!
Reference:
ZYNQ Development Platform FPGA Tutorial AX7020