Abstract: The
phase-locked loop (PLL) circuit is present in a variety of high frequency applications, local oscillator (LO) clock from the simple to the purification circuit for high-performance radio communication link, and a vector network analyzer (the VNA) in ultra-fast switching frequency synthesizer. Herein with reference to the above-described various applications introduce a PLL circuit module is constructed to guide the selection and application of the internal elements of each different trade-offs, which are helpful for novice and expert PLL. ADI's reference herein ADF4xxx HMCxxx series and a voltage controlled oscillator and PLL (VCO), and using ADIsimPLL (ADI's internal PLL circuit simulator) to show the different circuit performance parameters.
Basic configuration: clock circuitry purification
basic configuration is the phase locked loop reference signal (FREF) with the phase of the phase feedback signal (RFIN) F0 adjustable compared, as shown in FIG. In FIG 2 there is a work in the frequency domain negative feedback control loop path. When the comparison result in a steady state, i.e. ** output frequency and phase error detector input frequency and phase matching, we can say that the PLL is locked. ** For this article, we consider only the classical digital PLL architecture ADI's PLL ADF4xxx series achieved.
The first basic element of the circuit, a phase frequency detector (the PFD) . PFD input to the frequency and phase of the feedback REFIN to RFIN frequency and phase are compared. ADF4002 is a configurable independently PFD (feedback frequency divider N = 1) of the PLL. Thus, it can be used with high quality voltage controlled crystal oscillator (VCXO) and a narrow low-pass filter to purify high clock REFIN noise.
Phase frequency detector
FIG 3 phase frequency detector feedback signal FREF the + input terminal IN and -IN terminals are compared. It uses two D-type flip-flop and a delay element. Q way a positive current source output enable, another way to enable the Q output of negative current source. These so-called charge pump current source. More detailed information about the operation of the PFD, see the article "phase-locked loop for high-frequency receiver and transmitter."
使用這種架構，下面+IN端的輸入頻率高於-IN端（圖4），電荷泵輸出會推高電流，其在PLL低通濾波器中積分後，會使VCO調諧電壓上升。如此，-IN頻率將隨著VCO頻率的提高而提高，兩個PFD輸入最終會收斂或鎖定到相同頻率（圖5）。如果-IN頻率高於+IN頻率，則發生相反的情況。
高頻整數N分頻架構
為了產生一系列更高頻率，應使用VCO，其調諧範圍比VCXO更寬。這常用於跳頻或擴頻跳頻(FHSS)應用中。在這種PLL中，輸出是參考頻率的很多倍。壓控振盪器含有可變調諧元件，例如變容二極體，其電容隨輸入電壓而改變，形成一個可調諧振電路，從而可以產生一系列頻率（圖9）。PLL可以被認為是該VCO的控制系統。
回饋分頻器用於將VCO頻率分頻為PFD頻率，從而允許PLL生成PFD頻率倍數的輸出頻率。分頻器也可以用在參考路徑中，這樣就可以使用比PFD頻率更高的參考頻率。ADI的ADF4108就是這樣的PLL。PLL計數器是電路中要考慮的第二個基本元件。
PLL的關鍵性能參數是相位雜訊、頻率合成過程中的多餘副產物或雜散頻率（簡稱雜散）。對於整數N PLL分頻，雜散頻率由PFD頻率產生。來自電荷泵的漏電流會調變VCO的調諧埠。低通濾波器可減輕這種影響，而且頻寬越窄，對雜散頻率的濾波越強。理想單音訊號沒有雜訊或額外雜散頻率（圖10），但在實際應用中，相位雜訊像裙擺一樣出現在載波邊緣，如圖11所示。單邊頻相位雜訊是指在距離載波的指定頻率偏移處，1 Hz頻寬內相對於載波的雜訊功率。
整數N和小數N分頻器
在窄頻應用中，通道間隔很窄（通常<5MHz），回饋計數器N很高。透過使用雙模P/P + 1預分頻器，如圖12所示，可以利用一個小電路獲得高N值，並且N值可以利用公式N = PB + A來計算；以8/9預分頻器和90的N值為例，計算可得B值為11，A值為2。對於A或2個週期，雙模預分頻器將進行9分頻。對於剩餘的(B-A)或9個週期，它將進行8分頻，如表1所示。預分頻器一般利用較高頻率電路技術設計，例如雙極性射極耦合邏輯(ECL)電路，而A和B計數器可以接受這種較低頻率的預分頻器輸出，其可以利用低速CMOS電路製造，以減少電路面積和功耗。像ADF4002這樣的低頻淨化PLL省去了預分頻器。
頻內（PLL迴路路濾波器頻寬內）相位雜訊受N值直接影響，頻內雜訊增幅為20log(N)。因此，對於N值很高的窄頻應用，頻內雜訊主要由高N值決定。利用小數N分頻合成器（例如 ADF4159 或 HMC704），可以實現N值低得多但仍有精細解析度的系統。這樣一來，頻內相位雜訊可以大大降低。圖13至圖16說明了其實現原理。在這些示例中，使用兩個PLL來生成適合於5G系統本振(LO)的7.4 GHz至7.6 GHz頻率，通道解析度為1 MHz。ADF4108以整數N分頻配置使用（圖13），HMC704以小數N分頻配置使用。HMC704（圖14）可以使用50 MHz PFD頻率，這會降低N值，從而降低頻內雜訊，同時仍然支援1 MHz（或更小）的頻率步長——可注意到性能改善15 dB（在8 kHz偏移頻率處）（圖15與圖16對比）。但是，ADF4108必須使用1 MHz PFD才能實現相同的解析度。
** For the fractional-N PLL needs to be careful to ensure that spurious do not degrade system performance. ** For PLL HMC704 like, stray integral boundary (the fractional part is generated when the N value is close to 0 or 1, such as 147.98 or 148.02 148 very close to an integer value) of the most concern. The solution is the VCO output to the RF input buffering, and / or make careful frequency planning, frequency change REFIN prone to avoid problems.
The picture shows the integer frequency division
Fractional divider
references:
【1】https://www.analog.com/cn/design-center/landing-pages/002/tech-articles-taiwan/phase-locked-loop-pll-fundamentals.html#
