There are four LEDs on the PL side of the ZYNQ 7020 black gold development board, as shown in the figure below.
There are also four KEYs on the PL side, as shown in the figure below.
This article will match these four buttons with the four LEDs one by one. When the button is pressed or released, the corresponding LED will generate a light or dark signal.
Find the LED and KEY on the PL side in the schematic diagram as shown below.
By looking at the picture, we can see that the LED lights up when the key is low, and the key KEY is low when pressed. Therefore, the final presentation of this experiment should be: when the key is pressed, the corresponding LED lights up; when the key is released, the corresponding LED turns off. .
The code corresponding to this experiment is as follows.
module key_led(
input clk,
input [3:0] key, //keydown value is 0, keyup value is 1
output [3:0] led //led lighten when low
);
reg [3:0] led_d1; //define two D Flip-flop
reg [3:0] led_d2;
always@(posedge clk)
begin
led_d1 <= key;
end
always@(posedge clk)
begin
led_d2 <= led_d1;
end
assign led = led_d2;
endmodule
Two D flip-flops are added. The first-level D flip-flop records the status of the key after the rising edge of the clock arrives, and passes the status of the D flip-flop of this level to the second-level D flip-flop after the arrival of the next rising edge of the clock. The second stage D flip-flop then assigns the value to the LED.
The corresponding RTL diagram is shown in the figure below.
Before going to the development board for verification, first write the following simulation test code for simulation.
module key_led_sim();
reg clk;
reg [3:0] key;
wire [3:0] led;
initial
begin
clk = 0;
key = 4'b1111;
#250
key = 4'b1010;
#250
key = 4'b0101;
#250
key = 4'b0001;
end
always #10 clk = ~clk;
key_led uut_key_led(
.clk(clk),
.key(key),
.led(led)
);
endmodule
The simulation results are shown in the figure below.
From the above simulation results, we can see that the output of the LED is synchronized with the second-level D flip-flop and lags behind the first-level D flip-flop by one clock cycle. This is consistent with the preset. It can be verified on the development board. .
The pin assignments in this experiment can be made by referring to the table below.
port | pin |
---|---|
CLK | U18 |
KEY1 | N15 |
KEY2 | N16 |
KEY3 | T17 |
KEY4 | R17 |
LED1 | M14 |
LED2 | M15 |
LED3 | K16 |
LED4 | J16 |
The interface for assigning pins is shown in the figure below.
After the pin assignment is completed, the bitstream file can be generated and downloaded to the development board for on-board verification. The verification results on the development board are shown in the following animation.
When PL KEY1 (2/3/4) is pressed, the corresponding PL LED1 (2/3/4) lights up, and when released, the corresponding LED goes out.
The above is all the content of ZYNQ-button and LED correlation experiment!
Reference:
ZYNQ Development Platform FPGA Tutorial AX7020