PLL experiment under Vivado

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Preface

This section introduces a method of using Xilinx phase-locked loop. The AC7020 fpga development board I have has a 50MHz crystal oscillator connected to the PL end. The crystal oscillator output is linked to the global clock (MRCC) of the FPGA. This CLK can be used Driving the user logic circuit in the FPGA, the schematic diagram of the clock source is as shown in the figure:

But in our actual application, we may want to use a frequency of a specific size, such as 25MHz or 100MHz, then we can use Xilinx's lock The IP of the phase loop realizes its clock frequency division or multiplication.

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1. CMT (clock management unit)

1. Introduction to CMT

The clock resources in the Xilinx7 series devices include CMT (full name Clock Management Tile, namely clock management unit) . Each CMT consists of an MMCM (full name Mixed-Mode Clock Manager, namely mixed mode clock management) and a PLL (full name Phase Locked Loop) , that is, phase-locked loop),

• MMCM (Mixed Mode Clock Management) : It is a new mixed mode clock manager based on PLL, which achieves the lowest jitter and jitter filtering, providing higher performance clock management functions for high-performance FPGA designs.
  • MMCM adds a phase dynamic adjustment function based on PLL.
• PLL : It is a phase-locked loop or phase-locked loop, which is used to integrate clock signals to make high-frequency devices work normally, such as memory access data. PLL is used as a feedback technique in oscillators.
  • The phase-locked loop has powerful performance and can arbitrarily divide, multiply, phase, and duty cycle the clock signal input to the FPGA to output a desired clock;

MMCM 相对 PLL 的优势就是相位可以动态调整，但 PLL 占用的面积更小，而在大部分的设计当中大家使用 MMCM 或者 PLL 来对系统时钟进行分频、倍频和相位偏移都是完全可以的。

2. FPGA CMT block diagram

The figure below shows a simple structure of the 7 series FPGA CMT. The far left is some input clock sources, and the far right is the output.

3. MMCM block diagram

The figure below is the block diagram of MMCM. You can see that it contains 8 phase beats + 1 variable phase beat.

4. PLL block diagram

The figure below is the block diagram of the PLL. You can see that it only contains 8 phases.

2. Create project

1. Create a project

Create a project named pll_test

2. PLL IP core configuration

1. Click IP Catalog, search for clock, find Clocking Wizard and double-click it

. 2. Configure as shown below under Clocking Option.

• Primitive Select PLL
• Fill in the input frequency of the main clock in Input Clock Information with the crystal oscillator frequency of our board: 50MHz
  

3. Configure as shown below under Output Clocks, and click OK
to output four clocks of 200MHz, 100MHz, 50MHz, and 25MHz with different frequencies.

4. Click Generate

3. Instantiate

1. Create a file named pll_test.v

2. Copy the instantiation template to the pll_test.v file we just created

3. Modify the pll_test.v file. The modified code is as follows ( here we only output the 25MHz signal )

`timescale 1ns / 1ps

module pll_test(
    input sys_clk,  // 50MHz
    input rst_n,
    output clk_out
    );

wire pll_locked;    
    
    
clk_wiz_0 clk_inst
 (
  // Clock out ports
  .clk_out1(),     // output clk_out1
  .clk_out2(),     // output clk_out2
  .clk_out3(),     // output clk_out3
  .clk_out4(clk_out),     // output clk_out4
  // Status and control signals
  .reset(~rst_n), // input reset
  .locked(pll_locked),       // output locked
 // Clock in ports
  .clk_in1(sys_clk));      // input clk_in1  
    
endmodule

3. Carry out simulation

1. Create simulation files

Create a simulation file named vtf_pll_test.v and instantiate it to write a verilog simulation program

`timescale 1ns / 1ps

module vtf_pll_test;

reg sys_clk;
reg rst_n;
wire clk_out;

pll_test pll_inst(
    .sys_clk    (sys_clk),  // 50MHz
    .rst_n      (rst_n),
    .clk_out    (clk_out)
    );

initial 
begin
    sys_clk = 1'b0;
    rst_n = 1'b0;   // 对于按键来说我们进行的是低电平的一个复位
    # 100 rst_n = 1'b1;
end

always #10 sys_clk = ~sys_clk;  // 10ns 时钟翻转产生 25MHz 时钟

endmodule

2. Configure simulation settings

①. Right-click Run Simulation -> Simulation Settings...

②. Set the simulation time. Just fill in 200us here.

3. Conduct behavioral-level simulations

①. Left-click Run Simulation -> Run Behavioral Simulation

②. Drag clk_out1, clk_out2, clk_out3, clk_out_4, reset, and locked of clk_inst under pll_inst under vtf_pll_test to the Name column of the simulation interface. ③.

Click Run for 10us, you can see The results below

4. Hardware verification

1. Pin binding

1. Click "Open Elaborated Design", and then open the I/O Ports under Window

2. View the schematic diagram
①, T11 -> rst_n, T0 -> clk_out

②, U18 -> sys_clk

③, so the allocation is as follows:

④, proceed Save

⑤. The generated pll.xdc file is as shown below:

2. Generate bitstream file

①. Click "Generate Bitstream" to directly generate the bit file.

The following error appears:

[Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_inst/inst/clk_in1_clk_wiz_0] >

clk_inst/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X0Y15
 clk_inst/inst/plle2_adv_inst (PLLE2_ADV.CLKIN1) is provisionally placed by clockplacer on PLLE2_ADV_X0Y0

The above error could possibly be related to other connected instances. Following is a list of 
all the related clock rules and their respective instances.

Clock Rule: rule_pll_bufg
Status: PASS 
Rule Description: A PLL driving a BUFG must be placed on the same half side (top/bottom) of the device
 clk_inst/inst/plle2_adv_inst (PLLE2_ADV.CLKFBOUT) is provisionally placed by clockplacer on PLLE2_ADV_X0Y0
 and clk_inst/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y5

Just add this prompt to the XDC constraint file. The principle is to bypass the PAR check.

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_inst/inst/clk_in1_clk_wiz_0]

②. Select Open Hardware Manager and click OK

③. Plug in the fpga emulator and its power supply, select Auto Connect

④. Right-click xc7z020_1 -> Program Device

3. Verification

Find an oscilloscope and connect the probe to the T10 pin to check the output. You can see a 25MHz square wave signal.

5. Obtain resources by yourself

pll test based on vivado 2017.4

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My qq: 2442391036, welcome to communicate!

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