DW_APB_GPIO module DUT&Testbench simulation of ip test
Synopsys' gpio is a component of the DesignWare Advanced Peripheral Bus (DW_apb), confirming to ARM's AMBA specification 2.0. .
1. Learn to read DW_apb_gpio_databook (databook can be downloaded from the homepage)
In fact, we are very familiar with GPIO, which is widely used in ARM devices. We started to use it when using STM32 or Raspberry Pi. It is the most basic embedded interface. When used as input ports, we can read in external data through them. When used as output ports, we can output high or low levels through them to control the connected peripherals. In layman's terms, GPIO is used to control pins. So the experience of using GPIO in the past is also applicable here, we still operate GPIO through registers.
1.1 Overview:
Synopsys' DW_apb_gpio is an integral part of the DesignWare Advanced Peripheral Bus. Let's use this diagram to analyze the IP of gpio.
It can be seen that these small IPs can be connected to the APB bus . The APB advanced peripheral bus, as the name implies, is mainly used for the connection between low-bandwidth peripherals. For example, UART and GPIO can be connected to it. Unlike the high-performance bus, the advanced peripheral bus can support multiple main modules. The only main module in the APB is the APB bridge.
Going back to ip itself, registers are required to configure an IO. As a rule of thumb, we use configuration registers to select pin functions and data registers to read/write port data. Generally, when we use GPIO to control peripherals, we configure a certain pin as output or input, and then write 0 or 1 in the data register to make the pin output high or low level. If set to input, it is generally used for address control. The same is true in adb_gpio. For example, for the gpio_swporta_dr register, if some bits are set to output, the value of the register will be output.
1.2 Function:
The characteristics of DW_GPIO include: 1. Interface between APB and APB bridge
2. External data interface
3. Auxiliary hardware data interface
4. Interrupt interface
It is best to apply after the workspace is generated, and look at the component.v under src, such as what signals will be generated. Look inside the code to see how many signals are generated. Then he will also have annotations. For students who just read these IPs, if they can’t understand the annotations, they can be combined with the databook, and may also be combined with this Block Diagram. The block diagrams of other IPs are generally listed in the first part of the manual like GPIO. Chapter 1, there will be a DW_apb_component Block Diagram.
1.3 Features:
The characteristics of DW_GPIO include:
1. There are 128 independently configurable signals
2. Four ports from A to D can be configured separately
3. Each signal has a separate data register and data direction register
4. The configurable bit of each signal Hardware and Software Control
5. Configurable Interrupt Mode for Port A
6. Configurable Debounce Logic with External Slow Clock to Eliminate Bounce Interrupts
7. GPIO Component Type Register
8. GPIO Component Version Register
9. Output Signals on Configurable reset value
2. Simulation
Make preparations before the simulation and download the genuine Synopsys software coreConsultant.
2.1 Workspace Directory Contents：
Learn about the code structure, open coreConsultant, and view the generated code structure after creating Workspace.
Here I made a structure map, you can take a look:
2.2 Function Description：
The GPIO IP can be divided into software control mode and hardware control mode. In software control mode, the Direction of external I/O is controlled by writing to the Portx data direction register (gpio_swportx_ddr). The written data is transferred to the output signal gpio_portx_ddr of the DW_apb_gpio peripheral. External data is input through the external data signal gpio_ext_portx. Depending on whether gpio_ext_portx is configured as input or output, determine whether to read the value on the signal or read the data register of Portx.
In this mode, an auxiliary data input signal (aux_portx_out) and a direction control signal (aux_portx_en) [0 = Input; 1 = Output] are generated, where x is a, b, c or d.
2.3 Registers：
Chapter 6 of the data sheet records the offsets and corresponding descriptions of various Registers, which is convenient for us to configure the corresponding registers.
Let's take a look at a piece of code:
the corresponding offset and then test it.
2.4 Simulation results:
Enter the simulation link we are most concerned about, write the testbench, and then use coreConsultant to test:
for example, we configure the two registers gpio_inttype_level and gpio_int_polarity
to test the simulation results
Try another Testcase:
no problem. .
The above is the process of our small ip test, but to run through the connection between ARM and ASIC, we need to run through the software control process of each ip (ARM-AMBA connection test), and we will use DS5 and other software later. The installation of DS5 is especially The details, but it has already worked out, and I can write an article to share when I have time.
Download address of DW_apb_gpio_databook
: ( https://download.csdn.net/download/weixin_49457347/86309521 )