4 choose 1 data selector program and testbench file, give simulation waveform, analyze

1. Write the 4-to-1 data selector module code:

module mux4_1(out,in0,in1,in2,in3,sel);
 output out;
 input in0,in1,in2,in3;
 input[1:0] sel;
 reg out;
 always @(in0 or in1 or in2 or in3 or sel)//??????
  case(sel)
   2'b00: out=in0;
   2'b01: out=in1;
   2'b10: out=in2;
   2'b11: out=in3;
   default: out=2'bx;
 endcase
endmodule

2. Write the test file tmux4_1.v code:

`timescale  1ns/1ns  
module tmux4_1;
 reg in0, in1, in2, in3;
 reg [1:0] sel;
 wire out;

initial
  begin
   in0 = 1; in1 = 0; in2 = 0; in3 = 0; sel = 2'b00;
   #20 sel = 2'b01; #10 sel = 2'b10; #10 sel = 2'b11;   //stay 20ns when out=1
   #10 in0 = 0; in1 = 1; in2 = 0; in3 = 0; sel = 2'b01;
   #20 sel = 2'b00; #10 sel = 2'b10; #10 sel = 2'b11;
   #10 in0 = 0; in1 = 0; in2 = 1; in3 = 0; sel = 2'b10;
   #20 sel = 2'b00; #10 sel = 2'b11; #10 sel = 2'b01;
   #10 in0 = 0; in1 = 0; in2 = 0; in3 = 1; sel = 2'b11;
   #20 sel = 2'b00; #10 sel = 2'b01; #10 sel = 2'b10;
   #200 $stop;
   end

//exemplify
mux4_1  u0_mux4_1(
    .in0 (in0),
    .in1 (in1),
    .in2 (in2),
    .in3 (in3),
    .sel (sel),
    .out (out)
);

endmodule

Interpretation of the test code:
The output of the test code is divided into four cycles. In each cycle, control the sel value to select 4 input in values. Take the first cycle as an example, the duration is 50ns, in0 outputs 1, in1-3 outputs are all 0, sel selects in0 in the first 20ns, and then selects in1-3 one by one every 10ns, and other cycles are similar. In the second cycle, in1=1, in0, in2 and in3 are all 0, sel selects in1 to output for 20ns, and then selects in0, in2 and in3 to output for 10ns each.

3. Simulation results:
insert image description here
4. Analysis of simulation results:
The simulation waveforms are in0-3, sel and out from top to bottom. in0, in1, in2, and in3 output 1 in 50 ns in turn. Except for the input of output 1, all other 3 inputs output 0 at the current moment. In each cycle of input 1, select 20 ns output 1 in turn through sel, and select several other inputs. Each output 10ns, the experimental results are completely correct.

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Origin blog.csdn.net/qq_45362665/article/details/127203726