Unit Delay: Delay the signal by one sampling period
- The location in the simulation library is:
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Simulink / Discrete
HDL Coder / Discret
The model is:
Double-click the model to open the parameter setting interface, as shown in the figure:
illustrate
The Unit Delay block holds and delays the input by a specified sample period. When placed in an iteration subsystem, this block holds and delays its input by one iteration. This block is equivalent to the z-1 discrete-time operator. This block takes an input and generates an output. Each signal can be a scalar or a vector. If the input is a vector, the block holds and delays all elements in the vector by the same sampling period.