Computer Organization and Architecture
Flynn classification
Instructions and data Single / Double
CISC RISC
Simplified basic operation
Hierarchical storage structure
The speed of the memory arrangement
- cpu
- cache
- Memory (main memory)
- External memory
Fast memory capacity is usually small, large capacity memory is generally slower, mainly for cost considerations.
の purpose of introducing cache: cache is extremely small, but after adding the overall speed doubled.
Content stored by: a memory coupled to
vs memory address
Cache
Register> cache
Locality principle:
Temporal locality just finished another visit to visit
Access spatial locality near
Collection of set theory work processes frequently accessed pages
Calculating average cycle time:
Main memory
Classification: a read only memory random access memory ram rom
The former: no power-down data
The latter: No
Main memory - addressing
* 4 8-bit memory: address space of each eight bits of address space 4
Address unit requirements: (end address + 1- the first address) / 2 ^ 10
Calculate the number of bits stored
Disk structure and parameters
When the operation: Action && time-consuming
Access time = waiting time + seek time (positioning time + average rotational delay)
计算题
The concept of a single buffer
System Configuration and Performance Evaluation
Performance
Amdahl Solutions
Performance Evaluation Method
Clock frequency method: the reference speed CPU processing performance
Method instruction execution speed: how many per second, if only single algorithm adder
Equivalent instructions velocity method: improvement and the above average, arithmetic use
The data processing rate method PDR: only consider the optimization computing power, storage considerations
Comprehensive theoretical performance method CTP: each unit of measure
Benchmark method: run sub software, such as adding io measure, more comprehensive, widely used
Performance Testing
Monitoring software: Task Manager
Hardware monitoring:
Process Management
Process State
Predecessor graph
Walking cycling synchronized to the end
People in single mutex
Producer && consumers
Single buffer case
Multi-buffer case
PV operation
Critical Resource Resource exclusive access
Critical section to access the critical resource code
Semaphore s
Operation p -1 s <0
Operation v +1 s <= 0
pv operating Exercises
Predecessor graph
Before and after the first arrow v p
How many resources n * (k-1) +1
Deadlock
In the case of the banker's algorithm received back the loan lending again